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Create SDRAM Based FIFOs with the HERON-FPGA9 Module
- Standard IP that you can download to an HERON-FPGA9V module to create two large FIFOs with the memory interface of the DDR SDRAM providing the storage for the FIFO
- VHDL sources so that you can add your own FPGA design to this interface which uses only a small proportion of the FPGA resources
- Highly suitable for applications requiring buffering between high speed data sources
When combined with this standard bitstream, the HERON-FPGA9 splits the 256Kbytes of DDR SDRAM memory on the module into two equal parts. Each half is used to create an individual FIFO. These two 128Mbyte FIFOs interface to two separate pairs of HERON input and output FIFOs
The DDR memory of the HERON-FPGA9 enables high speed data storage with access speeds of 1.6Gbytes/sec possible per bank between the DDR and the FPGA. The data rate is demonstrated by the example.
The HERON-FPGA9 provides two 128Mbyte banks of DDR SDRAM memory. This memory is organised as two 32-bit wide memory interfaces, each with 32Mlocations. This example uses both banks to create two independent FIFOs of 32Mlocations by 32-bits. The first SDRAM FIFO reads and writes from HERON FIFO 0 while the second SDRAM FIFO reads and writes from HERON FIFO 1. When the HERON-FPGA9 is placed in a system with other modules and FIFOs from surrounding modules are correctly connected to FIFO 0 and FIFO 1, two large data buffers can be inserted in the flow of data through the system.
Functional Block Diagram
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