Home>>Product Information>>The HEART Architecture
HEART
A software configurable, inter-node communications system specifically designed for High Performance Real Time systems.
Hunt Engineering Architecture using Ring Technology - a standard architecture for our HERON module carriers meeting the needs of today's high performance real-time DSP systems.
The HEART communications concept is used for linking the blocks in your system. Those blocks can be DSP or I/O, it needs to be treated the same. Multi-processing, or single processor with I/O you need guaranteed bandwidth and latency.
You can read our paper on why we need HEART, but here is a summary of its features.
- HEART uses Virtual FIFO connections – once connected they behave just like a hardware FIFO, providing the status flags etc required by the HERON modules.
- The bandwidth of each Virtual FIFO is guaranteed in increments of 66 Mbytes/sec. If you need more than 66Mbytes/sec, then choose in increments of 66Mbytes/sec (timeslots) up to the full 400Mbytes/sec.
- Each node (including the Host Computer connection) have 6 independent input FIFOs and 6 independent output FIFOs.
- You can make multiple connections between the same nodes, so that different streams of data can be separated.
- Multi-cast connections are supported, where the data sent by a node can be received by more than one node.
- Connections can be pre-allocated at boot time, and then re-assigned by the application as necessary.
- Connections between boards are identical to connections within a board (depending on an extra inter-board module)
The virtual FIFO connections are configured using HUNT ENGINEERING supplied software tools that allow you to define your connectivity using a simple text file format. This file is the same file used by other HUNT ENGINEERING tools to load FPGAs, and boot DSPs – providing a fully integrated system management utility.
Embedded systems can use HSB to configure the connections at boot time using either a C6000 or FPGA module configured to perform that task from its boot ROM.
Once configured the connections guarantee the bandwidth is available at all times – there are no shared resources, so no arbitration uncertainties or delays are necessary.
Theoretically each module can carry 400Mbytes/sec of data in and out at the same time. There is a detailed discussion of what is really achievable but the performances can be summarised as :-
FPGA modules – 400Mbytes/sec in and 400Mbytes/sec out if
your FPGA design can process this amount of data
C6000 modules – One timeslot can sustain 65Mbytes/sec to
another C6000 or FPGA module. Adding more timeslots can achieve 230Mbytes/sec
sustained.
GDIO modules – These are 16 bit modules so have a maximum
of 200Mbytes/sec. Rates of 100Mbytes/sec can be sustained to a C6000 module, or
the full 200Mbytes/sec to an FPGA module.
PCI host interface – With the correct combination of PC
and operating system 100Mbytes/sec can be sustained.