-- ==============================================================
-- FILE : CAMLINK_IF.VHD  -  May be modified by the USER
-- ==============================================================
--
-- This file is part of the CameraLink IP for HERON-FPGA modules.
--
-- This file can be copied into a new project and modified by the
-- user to implement their own logic.
--
-- ==============================================================
--
--  Date        : 12/06/2006
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : Camera Link Interface
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    12-06-06    Developed from previous
--                                     Camera Link examples.
--  3.1     R. Williams    07-09-07    Changes to CamLink_IF.vhd
--                                     to ensure correct operation
--                                     under ISE9.1.
--  3.2     R. Williams    28-04-08    Improved timing margin of
--                                     camera clock signal for low
--                                     frequency option by using
--                                     an IDELAY component to
--                                     control clock timing.
--
-- ==============================================================


-- ==============================================================
--  Module      : CLINK
--  Description : Camera Link Interface module

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.numeric_std.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.vcomponents.ALL;
-- pragma translate_on


entity CLINK is
  generic ( LFreq_Deserialiser : boolean );
  port (
    RESET       : in  std_logic;
    CAM_CLK     : in  std_logic;
    CAM_DATA    : in  std_logic_vector(3 downto 0);
    POLARITY    : in  std_logic;
    USE_DVAL    : in  std_logic;
    BIT_SEL     : in  std_logic_vector(1 downto 0);
    PIXEL_CLOCK : out std_logic;
    DVALID_OUT  : out std_logic;
    EOL_OUT     : out std_logic;
    EOF_OUT     : out std_logic;
    DATA_OUT    : out std_logic_vector(31 downto 0);
    ACTIVE      : out std_logic_vector(3 downto 0)
  );
end CLINK;


architecture RTL of CLINK is

  component BUFG
    port(
      I : in  std_logic;
      O : out std_logic );
  end component;

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string  := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component LF_DFS_SUBM
    port (
      CLK_IN : in  std_logic;
      RST    : in  std_logic;
      CLKFX  : out std_logic;
      LOCK   : out std_logic );
  end component;

  component HF_DFS_SUBM
    port (
      CLK_IN : in  std_logic;
      RST    : in  std_logic;
      CLK0   : out std_logic;
      CLKFX  : out std_logic;
      LOCK   : out std_logic );
  end component;

  component LF_DES_1to7
    port (
      rst      : in  std_logic;
      rxclk1   : in  std_logic;
      rxclk35  : in  std_logic;
      cam_clk  : in  std_logic;
      data_in  : in  std_logic_vector(3 downto 0);
      data_out : out std_logic_vector(27 downto 0)
    );
  end component;

  component HF_DES_1to7
    port (
      rst      : in  std_logic;
      rxclk1   : in  std_logic;
      rxclk35  : in  std_logic;
      cam_clk  : in  std_logic;
      data_in  : in  std_logic_vector(3 downto 0);
      data_out : out std_logic_vector(27 downto 0)
    );
  end component;

  signal rxclk1  : std_logic;                     -- Serial clock x1
  signal rxclk35 : std_logic;                     -- Serial clock x3.5

  attribute keep : string;

  attribute keep of rxclk1     : signal is "true";
  attribute keep of rxclk35    : signal is "true";

  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute IOBDELAY_TYPE  of idel_clk : label is "FIXED";
  attribute IOBDELAY_VALUE of idel_clk : label is 25;

  signal GND      : std_logic;

  signal CLK_DEL  : std_logic;

  signal CL_LVAL  : std_logic;
  signal CL_FVAL  : std_logic;
  signal CL_DVAL  : std_logic;
  signal CL_SPARE : std_logic;
  signal LVAL_DEL : std_logic;
  signal FVAL_DEL : std_logic;
  signal DVALID   : std_logic;

  signal PORT_A   : std_logic_vector(7 downto 0);
  signal PORT_B   : std_logic_vector(7 downto 0);
  signal PORT_C   : std_logic_vector(7 downto 0);
  signal DATA     : std_logic_vector(31 downto 0);

  signal RXDATA   : std_logic_vector(27 downto 0);

  signal REG_DATA : std_logic_vector(15 downto 8);
  signal CounterA : std_logic_vector(3 downto 0);
  signal CounterB : std_logic_vector(3 downto 0);
  signal CounterC : std_logic_vector(3 downto 0);
  signal CounterD : std_logic_vector(3 downto 0);
  signal TcA      : std_logic;
  signal ActiveA  : std_logic;
  signal TcB      : std_logic;
  signal ActiveB  : std_logic;
  signal TcC      : std_logic;
  signal ActiveC  : std_logic;
  signal TcD      : std_logic;
  signal ActiveD  : std_logic;

begin

  EOL_OUT    <= ((CL_LVAL AND (NOT POLARITY)) OR ((NOT CL_LVAL) AND POLARITY)) AND FVAL_DEL AND LVAL_DEL;
  EOF_OUT    <= ((CL_FVAL AND (NOT POLARITY)) OR ((NOT CL_FVAL) AND POLARITY)) AND FVAL_DEL;

  DVALID_OUT <= DVALID;

  DVALID <= ((NOT POLARITY) AND (NOT CL_FVAL) AND (NOT CL_LVAL) AND
            ((USE_DVAL AND (NOT CL_DVAL)) OR (NOT USE_DVAL))  ) OR
            (     POLARITY  AND      CL_FVAL  AND      CL_LVAL  AND
            ((USE_DVAL AND      CL_DVAL ) OR (NOT USE_DVAL))  );

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      LVAL_DEL <= '0';
      FVAL_DEL <= '0';
    elsif rising_edge(rxclk1) then
      LVAL_DEL <= '0';
      FVAL_DEL <= '0';
      if (CL_LVAL='0' and POLARITY='0') or (CL_LVAL='1' and POLARITY='1') then
        LVAL_DEL <= '1';
      end if;
      if (CL_FVAL='0' and POLARITY='0') or (CL_FVAL='1' and POLARITY='1') then
        FVAL_DEL <= '1';
      end if;
    end if;
  end process;

  process(BIT_SEL, DATA)
  begin
    case BIT_SEL is
      when "00"   => DATA_OUT <= DATA;
      when "01"   => DATA_OUT <= "00" & DATA(31 downto 2);
      when "10"   => DATA_OUT <= "0000" & DATA(31 downto 4);
      when "11"   => DATA_OUT <= "000000" & DATA(31 downto 6);
      when others => DATA_OUT <= DATA;
    end case;
  end process;

  DATA  <= "00000000" & PORT_C & PORT_B & PORT_A;

  CL_LVAL   <= RXDATA(24);
  CL_FVAL   <= RXDATA(25);
  CL_DVAL   <= RXDATA(26);
  CL_SPARE  <= RXDATA(23);

  PORT_A(0) <= RXDATA(0);
  PORT_A(1) <= RXDATA(1);
  PORT_A(2) <= RXDATA(2);
  PORT_A(3) <= RXDATA(3);
  PORT_A(4) <= RXDATA(4);
  PORT_A(5) <= RXDATA(6);
  PORT_A(6) <= RXDATA(27);
  PORT_A(7) <= RXDATA(5);

  PORT_B(0) <= RXDATA(7);
  PORT_B(1) <= RXDATA(8);
  PORT_B(2) <= RXDATA(9);
  PORT_B(3) <= RXDATA(12);
  PORT_B(4) <= RXDATA(13);
  PORT_B(5) <= RXDATA(14);
  PORT_B(6) <= RXDATA(10);
  PORT_B(7) <= RXDATA(11);

  PORT_C(0) <= RXDATA(15);
  PORT_C(1) <= RXDATA(18);
  PORT_C(2) <= RXDATA(19);
  PORT_C(3) <= RXDATA(20);
  PORT_C(4) <= RXDATA(21);
  PORT_C(5) <= RXDATA(22);
  PORT_C(6) <= RXDATA(16);
  PORT_C(7) <= RXDATA(17);

  PIXEL_CLOCK <= rxclk1;

  idel_clk : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 25 )
    port map (
      O   => CLK_DEL,
      C   => GND,
      CE  => GND,
      I   => CAM_CLK,
      INC => GND,
      RST => GND );

  gLFREQ : if (LFreq_Deserialiser) generate

    -- Use a clock buffer to buffer CAM_CLK
    rxclk1_bufg  : bufg port map(i => CLK_DEL, o => rxclk1);

    -- Digital frequency synthesis sub-module
    idfs_dcm : LF_DFS_SUBM
      port map (
        CLK_IN => CLK_DEL,
        RST    => RESET,
        CLKFX  => rxclk35,
        LOCK   => open );

    -- Serial to 7 bit de-serialiser
    ilf_des_1to7 : LF_DES_1to7
      port map (
        rst      => RESET,
        rxclk1   => rxclk1,
        rxclk35  => rxclk35,
        cam_clk  => CAM_CLK,
        data_in  => CAM_DATA,
        data_out => RXDATA );

  end generate;  -- LFreq_Deserialiser=TRUE

  gHFREQ : if (NOT LFreq_Deserialiser) generate

    -- Digital frequency synthesis sub-module
    idfs_dcm : HF_DFS_SUBM
      port map (
        CLK_IN => CAM_CLK,
        RST    => RESET,
        CLK0   => rxclk1,
        CLKFX  => rxclk35,
        LOCK   => open );

    -- Serial to 7 bit de-serialiser
    ihf_des_1to7 : HF_DES_1to7
      port map (
        rst      => RESET,
        rxclk1   => rxclk1,
        rxclk35  => rxclk35,
        cam_clk  => CAM_CLK,
        data_in  => CAM_DATA,
        data_out => RXDATA );

  end generate;  -- LFreq_Deserialiser=FALSE

  -- Check active bits

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      REG_DATA(15 downto 8) <= (others=>'0');
    elsif rising_edge(rxclk1) then
      if DVALID='1' then
        REG_DATA(15 downto 8) <= DATA(15 downto 8);
      end if;
    end if;
  end process;

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      ActiveA  <= '0';
      CounterA <= (others=>'0');
    elsif rising_edge(rxclk1) then
      if TcA='1' then
        ActiveA  <= '1';
      end if;
      if DVALID='1' and REG_DATA(9)='1' and DATA(9)='0' then
        CounterA <= CounterA + 1;
      end if;
    end if;
  end process;

  TcA <= '1' when CounterA = "1111" else '0';

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      ActiveB  <= '0';
      CounterB <= (others=>'0');
    elsif rising_edge(rxclk1) then
      if TcB='1' then
        ActiveB  <= '1';
      end if;
      if DVALID='1' and REG_DATA(11)='1' and DATA(11)='0' then
        CounterB <= CounterB + 1;
      end if;
    end if;
  end process;

  TcB <= '1' when CounterB = "1111" else '0';

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      ActiveC  <= '0';
      CounterC <= (others=>'0');
    elsif rising_edge(rxclk1) then
      if TcC='1' then
        ActiveC  <= '1';
      end if;
      if DVALID='1' and REG_DATA(13)='1' and DATA(13)='0' then
        CounterC <= CounterC + 1;
      end if;
    end if;
  end process;

  TcC <= '1' when CounterC = "1111" else '0';

  process(RESET, rxclk1)
  begin
    if RESET='1' then
      ActiveD  <= '0';
      CounterD <= (others=>'0');
    elsif rising_edge(rxclk1) then
      if TcD='1' then
        ActiveD  <= '1';
      end if;
      if DVALID='1' and REG_DATA(15)='1' and DATA(15)='0' then
        CounterD <= CounterD + 1;
      end if;
    end if;
  end process;

  TcD <= '1' when CounterD = "1111" else '0';

  ACTIVE <= ActiveD & ActiveC & ActiveB & ActiveA;

end RTL;


-- ==============================================================
--  Module      : HF_DES_1TO7
--  Description : High frequency serial to 7-bit de-serialiser

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;

-- synopsys translate_off
library unisim;
  use unisim.vcomponents.all;
-- synopsys translate_on


entity HF_DES_1to7 is
  port (
    rst      : in  std_logic;
    rxclk1   : in  std_logic;
    rxclk35  : in  std_logic;
    cam_clk  : in  std_logic;
    data_in  : in  std_logic_vector(3 downto 0);
    data_out : out std_logic_vector(27 downto 0)
  );
end HF_DES_1to7;


architecture RTL of HF_DES_1to7 is

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FD
    port (
      Q : out std_logic;
      C : in  std_logic;
      D : in  std_logic );
  end component;

  component FDC
    port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CLR : in  std_logic );
  end component;

  component FDCE
    port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CE  : in  std_logic;
      CLR : in  std_logic );
  end component;

  component FDCE_1
   port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CE  : in  std_logic;
      CLR : in  std_logic );
  end component;

  attribute iob  : string;

  attribute iob of fd_sa : label is "true";

  attribute DDR_CLK_EDGE : string;
  attribute SRTYPE       : string;

  attribute DDR_CLK_EDGE of fd_pn0 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn1 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn2 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn3 : label is "OPPOSITE_EDGE";

  attribute SRTYPE of fd_pn0 : label is "SYNC";
  attribute SRTYPE of fd_pn1 : label is "SYNC";
  attribute SRTYPE of fd_pn2 : label is "SYNC";
  attribute SRTYPE of fd_pn3 : label is "SYNC";

  signal din_p   : std_logic_vector(3 downto 0);
  signal din_n   : std_logic_vector(3 downto 0);

  signal data_a  : std_logic_vector(27 downto 0);
  signal data_b  : std_logic_vector(27 downto 0);
  signal data_c  : std_logic_vector(27 downto 0);

  signal rdata_c : std_logic_vector(27 downto 0);
  signal rdata   : std_logic_vector(27 downto 0);

  signal sync_a  : std_logic;
  signal sync_b  : std_logic;
  signal sync_c  : std_logic;
  signal sync_d  : std_logic;
  signal sync_e  : std_logic;
  signal sync_f  : std_logic;
  signal sync_g  : std_logic;

  signal sel_d   : std_logic;
  signal sel     : std_logic;

  signal d00p    : std_logic;
  signal d00n    : std_logic;
  signal d01p    : std_logic;
  signal d01n    : std_logic;
  signal d02p    : std_logic;
  signal d02n    : std_logic;
  signal d03p    : std_logic;
  signal d03n    : std_logic;

  signal d10p    : std_logic;
  signal d10n    : std_logic;
  signal d11p    : std_logic;
  signal d11n    : std_logic;
  signal d12p    : std_logic;
  signal d12n    : std_logic;
  signal d13p    : std_logic;
  signal d13n    : std_logic;

  signal d20p    : std_logic;
  signal d20n    : std_logic;
  signal d21p    : std_logic;
  signal d21n    : std_logic;
  signal d22p    : std_logic;
  signal d22n    : std_logic;
  signal d23p    : std_logic;
  signal d23n    : std_logic;

  signal d30p    : std_logic;
  signal d30n    : std_logic;
  signal d31p    : std_logic;
  signal d31n    : std_logic;
  signal d32p    : std_logic;
  signal d32n    : std_logic;
  signal d33p    : std_logic;
  signal d33n    : std_logic;

  signal vcc     : std_logic;
  signal gnd     : std_logic;

begin

  vcc <= '1';
  gnd <= '0';

  -- Synchronisation logic
  fd_sa : fd port map (c => rxclk35, d => cam_clk, q => sync_a);
  fd_sb : fd port map (c => rxclk35, d => sync_a,  q => sync_b);

  sync_c <=      sync_a  and (not sync_b);
  sync_e <= (not sync_a) and (not sync_b);

  fd_sd : fd port map (c => rxclk35, d => sync_c, q => sync_d);
  fd_sf : fd port map (c => rxclk35, d => sync_e, q => sync_f);
  fd_sg : fd port map (c => rxclk35, d => sync_f, q => sync_g);

  sel_d <= not sync_g;

  fdnsy : fdce port map (c => rxclk35, d => sel_d, ce => sync_d, clr => rst, q => sel);

  -- IOB Flip-flops to register data on positive and negative edge of receiver clock x3.5
  fd_pn0 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(0),
      Q2 => din_n(0),
      C  => rxclk35,
      CE => vcc,
      D  => data_in(0),
      R  => GND,
      S  => GND );

  fd_pn1 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(1),
      Q2 => din_n(1),
      C  => rxclk35,
      CE => vcc,
      D  => data_in(1),
      R  => GND,
      S  => GND );

  fd_pn2 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(2),
      Q2 => din_n(2),
      C  => rxclk35,
      CE => vcc,
      D  => data_in(2),
      R  => GND,
      S  => GND );

  fd_pn3 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(3),
      Q2 => din_n(3),
      C  => rxclk35,
      CE => vcc,
      D  => data_in(3),
      R  => GND,
      S  => GND );


  fdc_d00p : fdc port map (c => rxclk35, d => din_p(0), clr => rst, q => d00p);
  fdc_d01p : fdc port map (c => rxclk35, d => d00p,     clr => rst, q => d01p);
  fdc_d02p : fdc port map (c => rxclk35, d => d01p,     clr => rst, q => d02p);
  fdc_d03p : fdc port map (c => rxclk35, d => d02p,     clr => rst, q => d03p);

  fdc_d00n : fdce_1 port map (c => rxclk35, d => din_n(0), clr => rst, q => d00n, ce => vcc);
  fdc_d01n : fdce_1 port map (c => rxclk35, d => d00n,     clr => rst, q => d01n, ce => vcc);
  fdc_d02n : fdce_1 port map (c => rxclk35, d => d01n,     clr => rst, q => d02n, ce => vcc);
  fdc_d03n : fdce_1 port map (c => rxclk35, d => d02n,     clr => rst, q => d03n, ce => vcc);

  fdc_d10p : fdc port map (c => rxclk35, d => din_p(1), clr => rst, q => d10p);
  fdc_d11p : fdc port map (c => rxclk35, d => d10p,     clr => rst, q => d11p);
  fdc_d12p : fdc port map (c => rxclk35, d => d11p,     clr => rst, q => d12p);
  fdc_d13p : fdc port map (c => rxclk35, d => d12p,     clr => rst, q => d13p);

  fdc_d10n : fdce_1 port map (c => rxclk35, d => din_n(1),  clr => rst, q => d10n, ce => vcc);
  fdc_d11n : fdce_1 port map (c => rxclk35, d => d10n,      clr => rst, q => d11n, ce => vcc);
  fdc_d12n : fdce_1 port map (c => rxclk35, d => d11n,      clr => rst, q => d12n, ce => vcc);
  fdc_d13n : fdce_1 port map (c => rxclk35, d => d12n,      clr => rst, q => d13n, ce => vcc);

  fdc_d20p : fdc port map (c => rxclk35, d => din_p(2), clr => rst, q => d20p);
  fdc_d21p : fdc port map (c => rxclk35, d => d20p,     clr => rst, q => d21p);
  fdc_d22p : fdc port map (c => rxclk35, d => d21p,     clr => rst, q => d22p);
  fdc_d23p : fdc port map (c => rxclk35, d => d22p,     clr => rst, q => d23p);

  fdc_d20n : fdce_1 port map (c => rxclk35, d => din_n(2), clr => rst, q => d20n, ce => vcc);
  fdc_d21n : fdce_1 port map (c => rxclk35, d => d20n,     clr => rst, q => d21n, ce => vcc);
  fdc_d22n : fdce_1 port map (c => rxclk35, d => d21n,     clr => rst, q => d22n, ce => vcc);
  fdc_d23n : fdce_1 port map (c => rxclk35, d => d22n,     clr => rst, q => d23n, ce => vcc);

  fdc_d30p : fdc port map (c => rxclk35, d => din_p(3), clr => rst, q => d30p);
  fdc_d31p : fdc port map (c => rxclk35, d => d30p,     clr => rst, q => d31p);
  fdc_d32p : fdc port map (c => rxclk35, d => d31p,     clr => rst, q => d32p);
  fdc_d33p : fdc port map (c => rxclk35, d => d32p,     clr => rst, q => d33p);

  fdc_d30n : fdce_1 port map (c => rxclk35, d => din_n(3), clr => rst, q => d30n, ce => vcc);
  fdc_d31n : fdce_1 port map (c => rxclk35, d => d30n,     clr => rst, q => d31n, ce => vcc);
  fdc_d32n : fdce_1 port map (c => rxclk35, d => d31n,     clr => rst, q => d32n, ce => vcc);
  fdc_d33n : fdce_1 port map (c => rxclk35, d => d32n,     clr => rst, q => d33n, ce => vcc);


  -- Bit sequence 0,1,2,3,4,6,7
  fdce_00p : fdce port map (c => rxclk35, d => d00p, ce => sync_d, clr => rst, q => data_a(0));
  fdce_01p : fdce port map (c => rxclk35, d => d01p, ce => sync_d, clr => rst, q => data_a(2));
  fdce_02p : fdce port map (c => rxclk35, d => d02p, ce => sync_d, clr => rst, q => data_a(4));
  fdce_03p : fdce port map (c => rxclk35, d => d03p, ce => sync_d, clr => rst, q => data_a(7));

  fdce_00n : fdce port map (c => rxclk35, d => d00n, ce => sync_c, clr => rst, q => data_b(1));
  fdce_01n : fdce port map (c => rxclk35, d => d01n, ce => sync_c, clr => rst, q => data_b(3));
  fdce_02n : fdce port map (c => rxclk35, d => d02n, ce => sync_c, clr => rst, q => data_b(6));

  fdce_03n : fdce port map (c => rxclk35, d => d00n, ce => sync_d, clr => rst, q => data_c(0));
  fdce_04n : fdce port map (c => rxclk35, d => d01n, ce => sync_d, clr => rst, q => data_c(2));
  fdce_05n : fdce port map (c => rxclk35, d => d02n, ce => sync_d, clr => rst, q => data_c(4));
  fdce_06n : fdce port map (c => rxclk35, d => d03n, ce => sync_d, clr => rst, q => data_c(7));

  -- Bit sequence 8,9,12,13,14,15,18
  fdce_10p : fdce port map (c => rxclk35, d => d10p, ce => sync_d, clr => rst, q => data_a(8));
  fdce_11p : fdce port map (c => rxclk35, d => d11p, ce => sync_d, clr => rst, q => data_a(12));
  fdce_12p : fdce port map (c => rxclk35, d => d12p, ce => sync_d, clr => rst, q => data_a(14));
  fdce_13p : fdce port map (c => rxclk35, d => d13p, ce => sync_d, clr => rst, q => data_a(18));

  fdce_10n : fdce port map (c => rxclk35, d => d10n, ce => sync_c, clr => rst, q => data_b(9));
  fdce_11n : fdce port map (c => rxclk35, d => d11n, ce => sync_c, clr => rst, q => data_b(13));
  fdce_12n : fdce port map (c => rxclk35, d => d12n, ce => sync_c, clr => rst, q => data_b(15));

  fdce_13n : fdce port map (c => rxclk35, d => d10n, ce => sync_d, clr => rst, q => data_c(8));
  fdce_14n : fdce port map (c => rxclk35, d => d11n, ce => sync_d, clr => rst, q => data_c(12));
  fdce_15n : fdce port map (c => rxclk35, d => d12n, ce => sync_d, clr => rst, q => data_c(14));
  fdce_16n : fdce port map (c => rxclk35, d => d13n, ce => sync_d, clr => rst, q => data_c(18));

  -- Bit sequence 19,20,21,22,24,25,26
  fdce_20p : fdce port map (c => rxclk35, d => d20p, ce => sync_d, clr => rst, q => data_a(19));
  fdce_21p : fdce port map (c => rxclk35, d => d21p, ce => sync_d, clr => rst, q => data_a(21));
  fdce_22p : fdce port map (c => rxclk35, d => d22p, ce => sync_d, clr => rst, q => data_a(24));
  fdce_23p : fdce port map (c => rxclk35, d => d23p, ce => sync_d, clr => rst, q => data_a(26));

  fdce_20n : fdce port map (c => rxclk35, d => d20n, ce => sync_c, clr => rst, q => data_b(20));
  fdce_21n : fdce port map (c => rxclk35, d => d21n, ce => sync_c, clr => rst, q => data_b(22));
  fdce_22n : fdce port map (c => rxclk35, d => d22n, ce => sync_c, clr => rst, q => data_b(25));

  fdce_23n : fdce port map (c => rxclk35, d => d20n, ce => sync_d, clr => rst, q => data_c(19));
  fdce_24n : fdce port map (c => rxclk35, d => d21n, ce => sync_d, clr => rst, q => data_c(21));
  fdce_25n : fdce port map (c => rxclk35, d => d22n, ce => sync_d, clr => rst, q => data_c(24));
  fdce_26n : fdce port map (c => rxclk35, d => d23n, ce => sync_d, clr => rst, q => data_c(26));

  -- Bit sequence 27,5,10,11,16,17,23
  fdce_30p : fdce port map (c => rxclk35, d => d30p, ce => sync_d, clr => rst, q => data_a(27));
  fdce_31p : fdce port map (c => rxclk35, d => d31p, ce => sync_d, clr => rst, q => data_a(10));
  fdce_32p : fdce port map (c => rxclk35, d => d32p, ce => sync_d, clr => rst, q => data_a(16));
  fdce_33p : fdce port map (c => rxclk35, d => d33p, ce => sync_d, clr => rst, q => data_a(23));

  fdce_30n : fdce port map (c => rxclk35, d => d30n, ce => sync_c, clr => rst, q => data_b(5));
  fdce_31n : fdce port map (c => rxclk35, d => d31n, ce => sync_c, clr => rst, q => data_b(11));
  fdce_32n : fdce port map (c => rxclk35, d => d32n, ce => sync_c, clr => rst, q => data_b(17));

  fdce_33n : fdce port map (c => rxclk35, d => d30n, ce => sync_d, clr => rst, q => data_c(27));
  fdce_34n : fdce port map (c => rxclk35, d => d31n, ce => sync_d, clr => rst, q => data_c(10));
  fdce_35n : fdce port map (c => rxclk35, d => d32n, ce => sync_d, clr => rst, q => data_c(16));
  fdce_36n : fdce port map (c => rxclk35, d => d33n, ce => sync_d, clr => rst, q => data_c(23));

  -- Bit sequence 0,1,2,3,4,6,7
  rdata_c(0) <= data_a(0) when sel='0' else data_c(0);
  rdata_c(1) <= data_b(1) when sel='0' else data_a(0);
  rdata_c(2) <= data_a(2) when sel='0' else data_c(2);
  rdata_c(3) <= data_b(3) when sel='0' else data_a(2);
  rdata_c(4) <= data_a(4) when sel='0' else data_c(4);
  rdata_c(6) <= data_b(6) when sel='0' else data_a(4);
  rdata_c(7) <= data_a(7) when sel='0' else data_c(7);

  -- Bit sequence 8,9,12,13,14,15,18
  rdata_c(8)  <= data_a(8)  when sel='0' else data_c(8);
  rdata_c(9)  <= data_b(9)  when sel='0' else data_a(8);
  rdata_c(12) <= data_a(12) when sel='0' else data_c(12);
  rdata_c(13) <= data_b(13) when sel='0' else data_a(12);
  rdata_c(14) <= data_a(14) when sel='0' else data_c(14);
  rdata_c(15) <= data_b(15) when sel='0' else data_a(14);
  rdata_c(18) <= data_a(18) when sel='0' else data_c(18);

  -- Bit sequence 19,20,21,22,24,25,26
  rdata_c(19) <= data_a(19) when sel='0' else data_c(19);
  rdata_c(20) <= data_b(20) when sel='0' else data_a(19);
  rdata_c(21) <= data_a(21) when sel='0' else data_c(21);
  rdata_c(22) <= data_b(22) when sel='0' else data_a(21);
  rdata_c(24) <= data_a(24) when sel='0' else data_c(24);
  rdata_c(25) <= data_b(25) when sel='0' else data_a(24);
  rdata_c(26) <= data_a(26) when sel='0' else data_c(26);

  -- Bit sequence 27,5,10,11,16,17,23
  rdata_c(27) <= data_a(27) when sel='0' else data_c(27);
  rdata_c(5)  <= data_b(5)  when sel='0' else data_a(27);
  rdata_c(10) <= data_a(10) when sel='0' else data_c(10);
  rdata_c(11) <= data_b(11) when sel='0' else data_a(10);
  rdata_c(16) <= data_a(16) when sel='0' else data_c(16);
  rdata_c(17) <= data_b(17) when sel='0' else data_a(16);
  rdata_c(23) <= data_a(23) when sel='0' else data_c(23);

  -- Bit sequence 0,1,2,3,4,6,7
  fdce_d0  : fdce port map (c => rxclk35, d => rdata_c(0),  ce => sync_c, clr => rst, q => rdata(0));
  fdce_d1  : fdce port map (c => rxclk35, d => rdata_c(1),  ce => sync_c, clr => rst, q => rdata(1));
  fdce_d2  : fdce port map (c => rxclk35, d => rdata_c(2),  ce => sync_c, clr => rst, q => rdata(2));
  fdce_d3  : fdce port map (c => rxclk35, d => rdata_c(3),  ce => sync_c, clr => rst, q => rdata(3));
  fdce_d4  : fdce port map (c => rxclk35, d => rdata_c(4),  ce => sync_c, clr => rst, q => rdata(4));
  fdce_d6  : fdce port map (c => rxclk35, d => rdata_c(6),  ce => sync_c, clr => rst, q => rdata(6));
  fdce_d7  : fdce port map (c => rxclk35, d => rdata_c(7),  ce => sync_c, clr => rst, q => rdata(7));

  -- Bit sequence 8,9,12,13,14,15,18
  fdce_d8  : fdce port map (c => rxclk35, d => rdata_c(8),  ce => sync_c, clr => rst, q => rdata(8));
  fdce_d9  : fdce port map (c => rxclk35, d => rdata_c(9),  ce => sync_c, clr => rst, q => rdata(9));
  fdce_d12 : fdce port map (c => rxclk35, d => rdata_c(12), ce => sync_c, clr => rst, q => rdata(12));
  fdce_d13 : fdce port map (c => rxclk35, d => rdata_c(13), ce => sync_c, clr => rst, q => rdata(13));
  fdce_d14 : fdce port map (c => rxclk35, d => rdata_c(14), ce => sync_c, clr => rst, q => rdata(14));
  fdce_d15 : fdce port map (c => rxclk35, d => rdata_c(15), ce => sync_c, clr => rst, q => rdata(15));
  fdce_d18 : fdce port map (c => rxclk35, d => rdata_c(18), ce => sync_c, clr => rst, q => rdata(18));

  -- Bit sequence 19,20,21,22,24,25,26
  fdce_d19 : fdce port map (c => rxclk35, d => rdata_c(19), ce => sync_c, clr => rst, q => rdata(19));
  fdce_d20 : fdce port map (c => rxclk35, d => rdata_c(20), ce => sync_c, clr => rst, q => rdata(20));
  fdce_d21 : fdce port map (c => rxclk35, d => rdata_c(21), ce => sync_c, clr => rst, q => rdata(21));
  fdce_d22 : fdce port map (c => rxclk35, d => rdata_c(22), ce => sync_c, clr => rst, q => rdata(22));
  fdce_d24 : fdce port map (c => rxclk35, d => rdata_c(24), ce => sync_c, clr => rst, q => rdata(24));
  fdce_d25 : fdce port map (c => rxclk35, d => rdata_c(25), ce => sync_c, clr => rst, q => rdata(25));
  fdce_d26 : fdce port map (c => rxclk35, d => rdata_c(26), ce => sync_c, clr => rst, q => rdata(26));

  -- Bit sequence 27,5,10,11,16,17,23
  fdce_d27 : fdce port map (c => rxclk35, d => rdata_c(27), ce => sync_c, clr => rst, q => rdata(27));
  fdce_d5  : fdce port map (c => rxclk35, d => rdata_c(5),  ce => sync_c, clr => rst, q => rdata(5));
  fdce_d10 : fdce port map (c => rxclk35, d => rdata_c(10), ce => sync_c, clr => rst, q => rdata(10));
  fdce_d11 : fdce port map (c => rxclk35, d => rdata_c(11), ce => sync_c, clr => rst, q => rdata(11));
  fdce_d16 : fdce port map (c => rxclk35, d => rdata_c(16), ce => sync_c, clr => rst, q => rdata(16));
  fdce_d17 : fdce port map (c => rxclk35, d => rdata_c(17), ce => sync_c, clr => rst, q => rdata(17));
  fdce_d23 : fdce port map (c => rxclk35, d => rdata_c(23), ce => sync_c, clr => rst, q => rdata(23));


  fdc_do0  : fdc port map (c => rxclk1, d => rdata(0),  clr => rst, q => data_out(0) );
  fdc_do1  : fdc port map (c => rxclk1, d => rdata(1),  clr => rst, q => data_out(1) );
  fdc_do2  : fdc port map (c => rxclk1, d => rdata(2),  clr => rst, q => data_out(2) );
  fdc_do3  : fdc port map (c => rxclk1, d => rdata(3),  clr => rst, q => data_out(3) );
  fdc_do4  : fdc port map (c => rxclk1, d => rdata(4),  clr => rst, q => data_out(4) );
  fdc_do6  : fdc port map (c => rxclk1, d => rdata(6),  clr => rst, q => data_out(6) );
  fdc_do7  : fdc port map (c => rxclk1, d => rdata(7),  clr => rst, q => data_out(7) );

  fdc_do8  : fdc port map (c => rxclk1, d => rdata(8),  clr => rst, q => data_out(8) );
  fdc_do9  : fdc port map (c => rxclk1, d => rdata(9),  clr => rst, q => data_out(9) );
  fdc_do12 : fdc port map (c => rxclk1, d => rdata(12), clr => rst, q => data_out(12));
  fdc_do13 : fdc port map (c => rxclk1, d => rdata(13), clr => rst, q => data_out(13));
  fdc_do14 : fdc port map (c => rxclk1, d => rdata(14), clr => rst, q => data_out(14));
  fdc_do15 : fdc port map (c => rxclk1, d => rdata(15), clr => rst, q => data_out(15));
  fdc_do18 : fdc port map (c => rxclk1, d => rdata(18), clr => rst, q => data_out(18));

  fdc_do19 : fdc port map (c => rxclk1, d => rdata(19), clr => rst, q => data_out(19));
  fdc_do20 : fdc port map (c => rxclk1, d => rdata(20), clr => rst, q => data_out(20));
  fdc_do21 : fdc port map (c => rxclk1, d => rdata(21), clr => rst, q => data_out(21));
  fdc_do22 : fdc port map (c => rxclk1, d => rdata(22), clr => rst, q => data_out(22));
  fdc_do24 : fdc port map (c => rxclk1, d => rdata(24), clr => rst, q => data_out(24));
  fdc_do25 : fdc port map (c => rxclk1, d => rdata(25), clr => rst, q => data_out(25));
  fdc_do26 : fdc port map (c => rxclk1, d => rdata(26), clr => rst, q => data_out(26));

  fdc_do27 : fdc port map (c => rxclk1, d => rdata(27), clr => rst, q => data_out(27));
  fdc_do5  : fdc port map (c => rxclk1, d => rdata(5),  clr => rst, q => data_out(5) );
  fdc_do10 : fdc port map (c => rxclk1, d => rdata(10), clr => rst, q => data_out(10));
  fdc_do11 : fdc port map (c => rxclk1, d => rdata(11), clr => rst, q => data_out(11));
  fdc_do16 : fdc port map (c => rxclk1, d => rdata(16), clr => rst, q => data_out(16));
  fdc_do17 : fdc port map (c => rxclk1, d => rdata(17), clr => rst, q => data_out(17));
  fdc_do23 : fdc port map (c => rxclk1, d => rdata(23), clr => rst, q => data_out(23));

end RTL;


-- ==============================================================
--  Module      : HF_DFS_SUBM
--  Description : High Frequency Option DFS module

library IEEE;
  use IEEE.std_logic_1164.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.VCOMPONENTS.all;
-- pragma translate_on


entity HF_DFS_SUBM is
  port (
    CLK_IN : in  std_logic;
    RST    : in  std_logic;
    CLK0   : out std_logic;
    CLKFX  : out std_logic;
    LOCK   : out std_logic
  );
end HF_DFS_SUBM;


architecture HF_DFS_SUBM_arch of HF_DFS_SUBM is

  component BUFG
    port (
      I : in  std_logic;
      O : out std_logic
    );
  end component;

  component DCM_ADV
    generic (
      CLK_FEEDBACK          : string     :=  "1X";
      CLKDV_DIVIDE          : real       :=  2.000000;
      CLKFX_DIVIDE          : integer    :=  1;
      CLKFX_MULTIPLY        : integer    :=  4;
      CLKIN_DIVIDE_BY_2     : boolean    :=  FALSE;
      CLKIN_PERIOD          : real       :=  0.000000;
      CLKOUT_PHASE_SHIFT    : string     :=  "NONE";
      DCM_AUTOCALIBRATION   : boolean    :=  TRUE;
      DCM_PERFORMANCE_MODE  : string     :=  "MAX_SPEED";
      DESKEW_ADJUST         : string     :=  "SYSTEM_SYNCHRONOUS";
      DFS_FREQUENCY_MODE    : string     :=  "LOW";
      DLL_FREQUENCY_MODE    : string     :=  "LOW";
      DUTY_CYCLE_CORRECTION : boolean    :=  TRUE;
      PHASE_SHIFT           : integer    :=  0;
      STARTUP_WAIT          : boolean    :=  FALSE;
      FACTORY_JF            : bit_vector :=  x"F0F0"
    );
    port (
      CLKIN    : in  std_logic;
      CLKFB    : in  std_logic;
      DADDR    : in  std_logic_vector(6 downto 0);
      DI       : in  std_logic_vector(15 downto 0);
      DWE      : in  std_logic;
      DEN      : in  std_logic;
      DCLK     : in  std_logic;
      RST      : in  std_logic;
      PSEN     : in  std_logic;
      PSINCDEC : in  std_logic;
      PSCLK    : in  std_logic;
      CLK0     : out std_logic;
      CLK90    : out std_logic;
      CLK180   : out std_logic;
      CLK270   : out std_logic;
      CLKDV    : out std_logic;
      CLK2X    : out std_logic;
      CLK2X180 : out std_logic;
      CLKFX    : out std_logic;
      CLKFX180 : out std_logic;
      DRDY     : out std_logic;
      DO       : out std_logic_vector(15 downto 0);
      LOCKED   : out std_logic;
      PSDONE   : out std_logic
    );
  end component;

  signal GND       : std_logic;

  signal CLK0_int  : std_logic;
  signal CLK0_buf  : std_logic;

  signal CLKFX_int : std_logic;
  signal CLKFX_buf : std_logic;

  signal GND_BUS   : std_logic_vector(15 downto 0);

begin

  GND <= '0';

  GND_BUS <= (others=>'0');

  iDCM_ADV : DCM_ADV
    generic map (
      CLK_FEEDBACK          => "1X",
      CLKDV_DIVIDE          => 2.0,
      CLKFX_DIVIDE          => 2,
      CLKFX_MULTIPLY        => 7,
      CLKIN_DIVIDE_BY_2     => FALSE,
      CLKIN_PERIOD          => 25.0,
      CLKOUT_PHASE_SHIFT    => "FIXED",
      DCM_AUTOCALIBRATION   => TRUE,
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
      DFS_FREQUENCY_MODE    => "LOW",
      DLL_FREQUENCY_MODE    => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF            => x"F0F0",
      PHASE_SHIFT           => 21,
      STARTUP_WAIT          => FALSE )
    port map (
      CLKIN    => CLK_IN,
      CLKFB    => CLK0_buf,
      DADDR    => GND_BUS(6 downto 0),
      DCLK     => GND,
      DEN      => GND,
      DI       => GND_BUS,
      DWE      => GND,
      PSCLK    => GND,
      PSEN     => GND,
      PSINCDEC => GND,
      RST      => RST,
      CLKDV    => open,
      CLKFX    => CLKFX_int,
      CLKFX180 => open,
      CLK0     => CLK0_int,
      CLK2X    => open,
      CLK2X180 => open,
      CLK90    => open,
      CLK180   => open,
      CLK270   => open,
      DO       => open,
      DRDY     => open,
      LOCKED   => LOCK,
      PSDONE   => open );

  iBUFG0 : BUFG port map (I=>CLK0_int, O=>CLK0_buf);

  iBUFG1 : BUFG port map (I=>CLKFX_int, O=>CLKFX_buf);

  CLK0  <= CLK0_buf;

  CLKFX <= CLKFX_buf;

end HF_DFS_SUBM_arch;


-- ==============================================================
--  Module      : LF_DES_1TO7
--  Description : Low frequency serial to 7-bit de-serialiser

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;

-- synopsys translate_off
library unisim;
  use unisim.vcomponents.all;
-- synopsys translate_on


entity LF_DES_1to7 is
  port (
    rst      : in  std_logic;
    rxclk1   : in  std_logic;
    rxclk35  : in  std_logic;
    cam_clk  : in  std_logic;
    data_in  : in  std_logic_vector(3 downto 0);
    data_out : out std_logic_vector(27 downto 0)
  );
end LF_DES_1to7;


architecture RTL of LF_DES_1to7 is

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string  := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FD
    port (
      Q : out std_logic;
      C : in  std_logic;
      D : in  std_logic );
  end component;

  component FDC
    port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CLR : in  std_logic );
  end component;

  component FDCE
    port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CE  : in  std_logic;
      CLR : in  std_logic );
  end component;

  component FDCE_1
   port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CE  : in  std_logic;
      CLR : in  std_logic );
  end component;

  attribute iob          : string;

  attribute iob of fd_sa : label is "true";

  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute IOBDELAY_TYPE  of idel_d0 : label is "FIXED";
  attribute IOBDELAY_TYPE  of idel_d1 : label is "FIXED";
  attribute IOBDELAY_TYPE  of idel_d2 : label is "FIXED";
  attribute IOBDELAY_TYPE  of idel_d3 : label is "FIXED";

  attribute IOBDELAY_VALUE of idel_d0 : label is 0;
  attribute IOBDELAY_VALUE of idel_d1 : label is 0;
  attribute IOBDELAY_VALUE of idel_d2 : label is 0;
  attribute IOBDELAY_VALUE of idel_d3 : label is 0;

  attribute DDR_CLK_EDGE : string;
  attribute SRTYPE       : string;

  attribute DDR_CLK_EDGE of fd_pn0 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn1 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn2 : label is "OPPOSITE_EDGE";
  attribute DDR_CLK_EDGE of fd_pn3 : label is "OPPOSITE_EDGE";

  attribute SRTYPE of fd_pn0 : label is "SYNC";
  attribute SRTYPE of fd_pn1 : label is "SYNC";
  attribute SRTYPE of fd_pn2 : label is "SYNC";
  attribute SRTYPE of fd_pn3 : label is "SYNC";

  signal din_p   : std_logic_vector(3 downto 0);
  signal din_n   : std_logic_vector(3 downto 0);
  signal din_del : std_logic_vector(3 downto 0);

  signal data_a  : std_logic_vector(27 downto 0);
  signal data_b  : std_logic_vector(27 downto 0);
  signal data_c  : std_logic_vector(27 downto 0);

  signal rdata_c : std_logic_vector(27 downto 0);
  signal rdata   : std_logic_vector(27 downto 0);

  signal sync_a  : std_logic;
  signal sync_b  : std_logic;
  signal sync_c  : std_logic;
  signal sync_d  : std_logic;
  signal sync_e  : std_logic;
  signal sync_f  : std_logic;
  signal sync_g  : std_logic;

  signal sel_d   : std_logic;
  signal sel     : std_logic;

  signal d00p    : std_logic;
  signal d00n    : std_logic;
  signal d01p    : std_logic;
  signal d01n    : std_logic;
  signal d02p    : std_logic;
  signal d02n    : std_logic;
  signal d03p    : std_logic;
  signal d03n    : std_logic;

  signal d10p    : std_logic;
  signal d10n    : std_logic;
  signal d11p    : std_logic;
  signal d11n    : std_logic;
  signal d12p    : std_logic;
  signal d12n    : std_logic;
  signal d13p    : std_logic;
  signal d13n    : std_logic;

  signal d20p    : std_logic;
  signal d20n    : std_logic;
  signal d21p    : std_logic;
  signal d21n    : std_logic;
  signal d22p    : std_logic;
  signal d22n    : std_logic;
  signal d23p    : std_logic;
  signal d23n    : std_logic;

  signal d30p    : std_logic;
  signal d30n    : std_logic;
  signal d31p    : std_logic;
  signal d31n    : std_logic;
  signal d32p    : std_logic;
  signal d32n    : std_logic;
  signal d33p    : std_logic;
  signal d33n    : std_logic;

  signal vcc     : std_logic;
  signal gnd     : std_logic;

begin

  vcc <= '1';
  gnd <= '0';

  -- Synchronisation logic
  fd_sa : fd port map (c => rxclk35, d => cam_clk, q => sync_a);
  fd_sb : fd port map (c => rxclk35, d => sync_a,  q => sync_b);

  sync_c <=      sync_a  and (not sync_b);
  sync_e <= (not sync_a) and (not sync_b);

  fd_sd : fd port map (c => rxclk35, d => sync_c, q => sync_d);
  fd_sf : fd port map (c => rxclk35, d => sync_e, q => sync_f);
  fd_sg : fd port map (c => rxclk35, d => sync_f, q => sync_g);

  sel_d <= not sync_g;

  fdnsy : fdce port map (c => rxclk35, d => sel_d, ce => sync_d, clr => rst, q => sel);

  idel_d0 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 0 )
    port map (
      O   => din_del(0),
      C   => GND,
      CE  => GND,
      I   => data_in(0),
      INC => GND,
      RST => GND );

  idel_d1 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 0 )
    port map (
      O   => din_del(1),
      C   => GND,
      CE  => GND,
      I   => data_in(1),
      INC => GND,
      RST => GND );

  idel_d2 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 0 )
    port map (
      O   => din_del(2),
      C   => GND,
      CE  => GND,
      I   => data_in(2),
      INC => GND,
      RST => GND );

  idel_d3 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 0 )
    port map (
      O   => din_del(3),
      C   => GND,
      CE  => GND,
      I   => data_in(3),
      INC => GND,
      RST => GND );

  -- IOB Flip-flops to register data on positive and negative edge of receiver clock x3.5
  fd_pn0 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(0),
      Q2 => din_n(0),
      C  => rxclk35,
      CE => vcc,
      D  => din_del(0),
      R  => GND,
      S  => GND );

  fd_pn1 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(1),
      Q2 => din_n(1),
      C  => rxclk35,
      CE => vcc,
      D  => din_del(1),
      R  => GND,
      S  => GND );

  fd_pn2 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(2),
      Q2 => din_n(2),
      C  => rxclk35,
      CE => vcc,
      D  => din_del(2),
      R  => GND,
      S  => GND );

  fd_pn3 : IDDR
    generic map (
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => din_p(3),
      Q2 => din_n(3),
      C  => rxclk35,
      CE => vcc,
      D  => din_del(3),
      R  => GND,
      S  => GND );


  fdc_d00p : fdc port map (c => rxclk35, d => din_p(0), clr => rst, q => d00p);
  fdc_d01p : fdc port map (c => rxclk35, d => d00p,     clr => rst, q => d01p);
  fdc_d02p : fdc port map (c => rxclk35, d => d01p,     clr => rst, q => d02p);
  fdc_d03p : fdc port map (c => rxclk35, d => d02p,     clr => rst, q => d03p);

  fdc_d00n : fdce_1 port map (c => rxclk35, d => din_n(0), clr => rst, q => d00n, ce => vcc);
  fdc_d01n : fdce_1 port map (c => rxclk35, d => d00n,     clr => rst, q => d01n, ce => vcc);
  fdc_d02n : fdce_1 port map (c => rxclk35, d => d01n,     clr => rst, q => d02n, ce => vcc);
  fdc_d03n : fdce_1 port map (c => rxclk35, d => d02n,     clr => rst, q => d03n, ce => vcc);

  fdc_d10p : fdc port map (c => rxclk35, d => din_p(1), clr => rst, q => d10p);
  fdc_d11p : fdc port map (c => rxclk35, d => d10p,     clr => rst, q => d11p);
  fdc_d12p : fdc port map (c => rxclk35, d => d11p,     clr => rst, q => d12p);
  fdc_d13p : fdc port map (c => rxclk35, d => d12p,     clr => rst, q => d13p);

  fdc_d10n : fdce_1 port map (c => rxclk35, d => din_n(1),  clr => rst, q => d10n, ce => vcc);
  fdc_d11n : fdce_1 port map (c => rxclk35, d => d10n,      clr => rst, q => d11n, ce => vcc);
  fdc_d12n : fdce_1 port map (c => rxclk35, d => d11n,      clr => rst, q => d12n, ce => vcc);
  fdc_d13n : fdce_1 port map (c => rxclk35, d => d12n,      clr => rst, q => d13n, ce => vcc);

  fdc_d20p : fdc port map (c => rxclk35, d => din_p(2), clr => rst, q => d20p);
  fdc_d21p : fdc port map (c => rxclk35, d => d20p,     clr => rst, q => d21p);
  fdc_d22p : fdc port map (c => rxclk35, d => d21p,     clr => rst, q => d22p);
  fdc_d23p : fdc port map (c => rxclk35, d => d22p,     clr => rst, q => d23p);

  fdc_d20n : fdce_1 port map (c => rxclk35, d => din_n(2), clr => rst, q => d20n, ce => vcc);
  fdc_d21n : fdce_1 port map (c => rxclk35, d => d20n,     clr => rst, q => d21n, ce => vcc);
  fdc_d22n : fdce_1 port map (c => rxclk35, d => d21n,     clr => rst, q => d22n, ce => vcc);
  fdc_d23n : fdce_1 port map (c => rxclk35, d => d22n,     clr => rst, q => d23n, ce => vcc);

  fdc_d30p : fdc port map (c => rxclk35, d => din_p(3), clr => rst, q => d30p);
  fdc_d31p : fdc port map (c => rxclk35, d => d30p,     clr => rst, q => d31p);
  fdc_d32p : fdc port map (c => rxclk35, d => d31p,     clr => rst, q => d32p);
  fdc_d33p : fdc port map (c => rxclk35, d => d32p,     clr => rst, q => d33p);

  fdc_d30n : fdce_1 port map (c => rxclk35, d => din_n(3), clr => rst, q => d30n, ce => vcc);
  fdc_d31n : fdce_1 port map (c => rxclk35, d => d30n,     clr => rst, q => d31n, ce => vcc);
  fdc_d32n : fdce_1 port map (c => rxclk35, d => d31n,     clr => rst, q => d32n, ce => vcc);
  fdc_d33n : fdce_1 port map (c => rxclk35, d => d32n,     clr => rst, q => d33n, ce => vcc);


  -- Bit sequence 0,1,2,3,4,6,7
  fdce_00p : fdce port map (c => rxclk35, d => d00p, ce => sync_d, clr => rst, q => data_a(0));
  fdce_01p : fdce port map (c => rxclk35, d => d01p, ce => sync_d, clr => rst, q => data_a(2));
  fdce_02p : fdce port map (c => rxclk35, d => d02p, ce => sync_d, clr => rst, q => data_a(4));
  fdce_03p : fdce port map (c => rxclk35, d => d03p, ce => sync_d, clr => rst, q => data_a(7));

  fdce_00n : fdce port map (c => rxclk35, d => d00n, ce => sync_c, clr => rst, q => data_b(1));
  fdce_01n : fdce port map (c => rxclk35, d => d01n, ce => sync_c, clr => rst, q => data_b(3));
  fdce_02n : fdce port map (c => rxclk35, d => d02n, ce => sync_c, clr => rst, q => data_b(6));

  fdce_03n : fdce port map (c => rxclk35, d => d00n, ce => sync_d, clr => rst, q => data_c(0));
  fdce_04n : fdce port map (c => rxclk35, d => d01n, ce => sync_d, clr => rst, q => data_c(2));
  fdce_05n : fdce port map (c => rxclk35, d => d02n, ce => sync_d, clr => rst, q => data_c(4));
  fdce_06n : fdce port map (c => rxclk35, d => d03n, ce => sync_d, clr => rst, q => data_c(7));

  -- Bit sequence 8,9,12,13,14,15,18
  fdce_10p : fdce port map (c => rxclk35, d => d10p, ce => sync_d, clr => rst, q => data_a(8));
  fdce_11p : fdce port map (c => rxclk35, d => d11p, ce => sync_d, clr => rst, q => data_a(12));
  fdce_12p : fdce port map (c => rxclk35, d => d12p, ce => sync_d, clr => rst, q => data_a(14));
  fdce_13p : fdce port map (c => rxclk35, d => d13p, ce => sync_d, clr => rst, q => data_a(18));

  fdce_10n : fdce port map (c => rxclk35, d => d10n, ce => sync_c, clr => rst, q => data_b(9));
  fdce_11n : fdce port map (c => rxclk35, d => d11n, ce => sync_c, clr => rst, q => data_b(13));
  fdce_12n : fdce port map (c => rxclk35, d => d12n, ce => sync_c, clr => rst, q => data_b(15));

  fdce_13n : fdce port map (c => rxclk35, d => d10n, ce => sync_d, clr => rst, q => data_c(8));
  fdce_14n : fdce port map (c => rxclk35, d => d11n, ce => sync_d, clr => rst, q => data_c(12));
  fdce_15n : fdce port map (c => rxclk35, d => d12n, ce => sync_d, clr => rst, q => data_c(14));
  fdce_16n : fdce port map (c => rxclk35, d => d13n, ce => sync_d, clr => rst, q => data_c(18));

  -- Bit sequence 19,20,21,22,24,25,26
  fdce_20p : fdce port map (c => rxclk35, d => d20p, ce => sync_d, clr => rst, q => data_a(19));
  fdce_21p : fdce port map (c => rxclk35, d => d21p, ce => sync_d, clr => rst, q => data_a(21));
  fdce_22p : fdce port map (c => rxclk35, d => d22p, ce => sync_d, clr => rst, q => data_a(24));
  fdce_23p : fdce port map (c => rxclk35, d => d23p, ce => sync_d, clr => rst, q => data_a(26));

  fdce_20n : fdce port map (c => rxclk35, d => d20n, ce => sync_c, clr => rst, q => data_b(20));
  fdce_21n : fdce port map (c => rxclk35, d => d21n, ce => sync_c, clr => rst, q => data_b(22));
  fdce_22n : fdce port map (c => rxclk35, d => d22n, ce => sync_c, clr => rst, q => data_b(25));

  fdce_23n : fdce port map (c => rxclk35, d => d20n, ce => sync_d, clr => rst, q => data_c(19));
  fdce_24n : fdce port map (c => rxclk35, d => d21n, ce => sync_d, clr => rst, q => data_c(21));
  fdce_25n : fdce port map (c => rxclk35, d => d22n, ce => sync_d, clr => rst, q => data_c(24));
  fdce_26n : fdce port map (c => rxclk35, d => d23n, ce => sync_d, clr => rst, q => data_c(26));

  -- Bit sequence 27,5,10,11,16,17,23
  fdce_30p : fdce port map (c => rxclk35, d => d30p, ce => sync_d, clr => rst, q => data_a(27));
  fdce_31p : fdce port map (c => rxclk35, d => d31p, ce => sync_d, clr => rst, q => data_a(10));
  fdce_32p : fdce port map (c => rxclk35, d => d32p, ce => sync_d, clr => rst, q => data_a(16));
  fdce_33p : fdce port map (c => rxclk35, d => d33p, ce => sync_d, clr => rst, q => data_a(23));

  fdce_30n : fdce port map (c => rxclk35, d => d30n, ce => sync_c, clr => rst, q => data_b(5));
  fdce_31n : fdce port map (c => rxclk35, d => d31n, ce => sync_c, clr => rst, q => data_b(11));
  fdce_32n : fdce port map (c => rxclk35, d => d32n, ce => sync_c, clr => rst, q => data_b(17));

  fdce_33n : fdce port map (c => rxclk35, d => d30n, ce => sync_d, clr => rst, q => data_c(27));
  fdce_34n : fdce port map (c => rxclk35, d => d31n, ce => sync_d, clr => rst, q => data_c(10));
  fdce_35n : fdce port map (c => rxclk35, d => d32n, ce => sync_d, clr => rst, q => data_c(16));
  fdce_36n : fdce port map (c => rxclk35, d => d33n, ce => sync_d, clr => rst, q => data_c(23));

  -- Bit sequence 0,1,2,3,4,6,7
  rdata_c(0) <= data_a(0) when sel='0' else data_c(0);
  rdata_c(1) <= data_b(1) when sel='0' else data_a(0);
  rdata_c(2) <= data_a(2) when sel='0' else data_c(2);
  rdata_c(3) <= data_b(3) when sel='0' else data_a(2);
  rdata_c(4) <= data_a(4) when sel='0' else data_c(4);
  rdata_c(6) <= data_b(6) when sel='0' else data_a(4);
  rdata_c(7) <= data_a(7) when sel='0' else data_c(7);

  -- Bit sequence 8,9,12,13,14,15,18
  rdata_c(8)  <= data_a(8)  when sel='0' else data_c(8);
  rdata_c(9)  <= data_b(9)  when sel='0' else data_a(8);
  rdata_c(12) <= data_a(12) when sel='0' else data_c(12);
  rdata_c(13) <= data_b(13) when sel='0' else data_a(12);
  rdata_c(14) <= data_a(14) when sel='0' else data_c(14);
  rdata_c(15) <= data_b(15) when sel='0' else data_a(14);
  rdata_c(18) <= data_a(18) when sel='0' else data_c(18);

  -- Bit sequence 19,20,21,22,24,25,26
  rdata_c(19) <= data_a(19) when sel='0' else data_c(19);
  rdata_c(20) <= data_b(20) when sel='0' else data_a(19);
  rdata_c(21) <= data_a(21) when sel='0' else data_c(21);
  rdata_c(22) <= data_b(22) when sel='0' else data_a(21);
  rdata_c(24) <= data_a(24) when sel='0' else data_c(24);
  rdata_c(25) <= data_b(25) when sel='0' else data_a(24);
  rdata_c(26) <= data_a(26) when sel='0' else data_c(26);

  -- Bit sequence 27,5,10,11,16,17,23
  rdata_c(27) <= data_a(27) when sel='0' else data_c(27);
  rdata_c(5)  <= data_b(5)  when sel='0' else data_a(27);
  rdata_c(10) <= data_a(10) when sel='0' else data_c(10);
  rdata_c(11) <= data_b(11) when sel='0' else data_a(10);
  rdata_c(16) <= data_a(16) when sel='0' else data_c(16);
  rdata_c(17) <= data_b(17) when sel='0' else data_a(16);
  rdata_c(23) <= data_a(23) when sel='0' else data_c(23);

  -- Bit sequence 0,1,2,3,4,6,7
  fdce_d0  : fdce port map (c => rxclk35, d => rdata_c(0),  ce => sync_c, clr => rst, q => rdata(0));
  fdce_d1  : fdce port map (c => rxclk35, d => rdata_c(1),  ce => sync_c, clr => rst, q => rdata(1));
  fdce_d2  : fdce port map (c => rxclk35, d => rdata_c(2),  ce => sync_c, clr => rst, q => rdata(2));
  fdce_d3  : fdce port map (c => rxclk35, d => rdata_c(3),  ce => sync_c, clr => rst, q => rdata(3));
  fdce_d4  : fdce port map (c => rxclk35, d => rdata_c(4),  ce => sync_c, clr => rst, q => rdata(4));
  fdce_d6  : fdce port map (c => rxclk35, d => rdata_c(6),  ce => sync_c, clr => rst, q => rdata(6));
  fdce_d7  : fdce port map (c => rxclk35, d => rdata_c(7),  ce => sync_c, clr => rst, q => rdata(7));

  -- Bit sequence 8,9,12,13,14,15,18
  fdce_d8  : fdce port map (c => rxclk35, d => rdata_c(8),  ce => sync_c, clr => rst, q => rdata(8));
  fdce_d9  : fdce port map (c => rxclk35, d => rdata_c(9),  ce => sync_c, clr => rst, q => rdata(9));
  fdce_d12 : fdce port map (c => rxclk35, d => rdata_c(12), ce => sync_c, clr => rst, q => rdata(12));
  fdce_d13 : fdce port map (c => rxclk35, d => rdata_c(13), ce => sync_c, clr => rst, q => rdata(13));
  fdce_d14 : fdce port map (c => rxclk35, d => rdata_c(14), ce => sync_c, clr => rst, q => rdata(14));
  fdce_d15 : fdce port map (c => rxclk35, d => rdata_c(15), ce => sync_c, clr => rst, q => rdata(15));
  fdce_d18 : fdce port map (c => rxclk35, d => rdata_c(18), ce => sync_c, clr => rst, q => rdata(18));

  -- Bit sequence 19,20,21,22,24,25,26
  fdce_d19 : fdce port map (c => rxclk35, d => rdata_c(19), ce => sync_c, clr => rst, q => rdata(19));
  fdce_d20 : fdce port map (c => rxclk35, d => rdata_c(20), ce => sync_c, clr => rst, q => rdata(20));
  fdce_d21 : fdce port map (c => rxclk35, d => rdata_c(21), ce => sync_c, clr => rst, q => rdata(21));
  fdce_d22 : fdce port map (c => rxclk35, d => rdata_c(22), ce => sync_c, clr => rst, q => rdata(22));
  fdce_d24 : fdce port map (c => rxclk35, d => rdata_c(24), ce => sync_c, clr => rst, q => rdata(24));
  fdce_d25 : fdce port map (c => rxclk35, d => rdata_c(25), ce => sync_c, clr => rst, q => rdata(25));
  fdce_d26 : fdce port map (c => rxclk35, d => rdata_c(26), ce => sync_c, clr => rst, q => rdata(26));

  -- Bit sequence 27,5,10,11,16,17,23
  fdce_d27 : fdce port map (c => rxclk35, d => rdata_c(27), ce => sync_c, clr => rst, q => rdata(27));
  fdce_d5  : fdce port map (c => rxclk35, d => rdata_c(5),  ce => sync_c, clr => rst, q => rdata(5));
  fdce_d10 : fdce port map (c => rxclk35, d => rdata_c(10), ce => sync_c, clr => rst, q => rdata(10));
  fdce_d11 : fdce port map (c => rxclk35, d => rdata_c(11), ce => sync_c, clr => rst, q => rdata(11));
  fdce_d16 : fdce port map (c => rxclk35, d => rdata_c(16), ce => sync_c, clr => rst, q => rdata(16));
  fdce_d17 : fdce port map (c => rxclk35, d => rdata_c(17), ce => sync_c, clr => rst, q => rdata(17));
  fdce_d23 : fdce port map (c => rxclk35, d => rdata_c(23), ce => sync_c, clr => rst, q => rdata(23));


  fdc_do0  : fdc port map (c => rxclk1, d => rdata(0),  clr => rst, q => data_out(0) );
  fdc_do1  : fdc port map (c => rxclk1, d => rdata(1),  clr => rst, q => data_out(1) );
  fdc_do2  : fdc port map (c => rxclk1, d => rdata(2),  clr => rst, q => data_out(2) );
  fdc_do3  : fdc port map (c => rxclk1, d => rdata(3),  clr => rst, q => data_out(3) );
  fdc_do4  : fdc port map (c => rxclk1, d => rdata(4),  clr => rst, q => data_out(4) );
  fdc_do6  : fdc port map (c => rxclk1, d => rdata(6),  clr => rst, q => data_out(6) );
  fdc_do7  : fdc port map (c => rxclk1, d => rdata(7),  clr => rst, q => data_out(7) );

  fdc_do8  : fdc port map (c => rxclk1, d => rdata(8),  clr => rst, q => data_out(8) );
  fdc_do9  : fdc port map (c => rxclk1, d => rdata(9),  clr => rst, q => data_out(9) );
  fdc_do12 : fdc port map (c => rxclk1, d => rdata(12), clr => rst, q => data_out(12));
  fdc_do13 : fdc port map (c => rxclk1, d => rdata(13), clr => rst, q => data_out(13));
  fdc_do14 : fdc port map (c => rxclk1, d => rdata(14), clr => rst, q => data_out(14));
  fdc_do15 : fdc port map (c => rxclk1, d => rdata(15), clr => rst, q => data_out(15));
  fdc_do18 : fdc port map (c => rxclk1, d => rdata(18), clr => rst, q => data_out(18));

  fdc_do19 : fdc port map (c => rxclk1, d => rdata(19), clr => rst, q => data_out(19));
  fdc_do20 : fdc port map (c => rxclk1, d => rdata(20), clr => rst, q => data_out(20));
  fdc_do21 : fdc port map (c => rxclk1, d => rdata(21), clr => rst, q => data_out(21));
  fdc_do22 : fdc port map (c => rxclk1, d => rdata(22), clr => rst, q => data_out(22));
  fdc_do24 : fdc port map (c => rxclk1, d => rdata(24), clr => rst, q => data_out(24));
  fdc_do25 : fdc port map (c => rxclk1, d => rdata(25), clr => rst, q => data_out(25));
  fdc_do26 : fdc port map (c => rxclk1, d => rdata(26), clr => rst, q => data_out(26));

  fdc_do27 : fdc port map (c => rxclk1, d => rdata(27), clr => rst, q => data_out(27));
  fdc_do5  : fdc port map (c => rxclk1, d => rdata(5),  clr => rst, q => data_out(5) );
  fdc_do10 : fdc port map (c => rxclk1, d => rdata(10), clr => rst, q => data_out(10));
  fdc_do11 : fdc port map (c => rxclk1, d => rdata(11), clr => rst, q => data_out(11));
  fdc_do16 : fdc port map (c => rxclk1, d => rdata(16), clr => rst, q => data_out(16));
  fdc_do17 : fdc port map (c => rxclk1, d => rdata(17), clr => rst, q => data_out(17));
  fdc_do23 : fdc port map (c => rxclk1, d => rdata(23), clr => rst, q => data_out(23));

end RTL;


-- ==============================================================
--  Module      : LF_DFS_SUBM
--  Description : Low Frequency Option DFS module

library IEEE;
  use IEEE.std_logic_1164.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.VCOMPONENTS.all;
-- pragma translate_on


entity LF_DFS_SUBM is
  port (
    CLK_IN : in  std_logic;
    RST    : in  std_logic;
    CLKFX  : out std_logic;
    LOCK   : out std_logic
  );
end LF_DFS_SUBM;


architecture LF_DFS_SUBM_arch of LF_DFS_SUBM is

  component BUFG
    port (
      I : in  std_logic;
      O : out std_logic
    );
  end component;

  component DCM_ADV
    generic (
      CLK_FEEDBACK          : string     :=  "1X";
      CLKDV_DIVIDE          : real       :=  2.000000;
      CLKFX_DIVIDE          : integer    :=  1;
      CLKFX_MULTIPLY        : integer    :=  4;
      CLKIN_DIVIDE_BY_2     : boolean    :=  FALSE;
      CLKIN_PERIOD          : real       :=  0.000000;
      CLKOUT_PHASE_SHIFT    : string     :=  "NONE";
      DCM_AUTOCALIBRATION   : boolean    :=  TRUE;
      DCM_PERFORMANCE_MODE  : string     :=  "MAX_SPEED";
      DESKEW_ADJUST         : string     :=  "SYSTEM_SYNCHRONOUS";
      DFS_FREQUENCY_MODE    : string     :=  "LOW";
      DLL_FREQUENCY_MODE    : string     :=  "LOW";
      DUTY_CYCLE_CORRECTION : boolean    :=  TRUE;
      PHASE_SHIFT           : integer    :=  0;
      STARTUP_WAIT          : boolean    :=  FALSE;
      FACTORY_JF            : bit_vector :=  x"F0F0"
    );
    port (
      CLKIN    : in  std_logic;
      CLKFB    : in  std_logic;
      DADDR    : in  std_logic_vector(6 downto 0);
      DI       : in  std_logic_vector(15 downto 0);
      DWE      : in  std_logic;
      DEN      : in  std_logic;
      DCLK     : in  std_logic;
      RST      : in  std_logic;
      PSEN     : in  std_logic;
      PSINCDEC : in  std_logic;
      PSCLK    : in  std_logic;
      CLK0     : out std_logic;
      CLK90    : out std_logic;
      CLK180   : out std_logic;
      CLK270   : out std_logic;
      CLKDV    : out std_logic;
      CLK2X    : out std_logic;
      CLK2X180 : out std_logic;
      CLKFX    : out std_logic;
      CLKFX180 : out std_logic;
      DRDY     : out std_logic;
      DO       : out std_logic_vector(15 downto 0);
      LOCKED   : out std_logic;
      PSDONE   : out std_logic
    );
  end component;

  signal GND       : std_logic;

  signal CLKFX_int : std_logic;
  signal CLKFX_buf : std_logic;

  signal GND_BUS   : std_logic_vector(15 downto 0);

begin

  GND <= '0';

  GND_BUS <= (others=>'0');

  iDCM_ADV : DCM_ADV
    generic map (
      CLK_FEEDBACK          => "1X",
      CLKDV_DIVIDE          => 2.0,
      CLKFX_DIVIDE          => 2,
      CLKFX_MULTIPLY        => 7,
      CLKIN_DIVIDE_BY_2     => FALSE,
      CLKIN_PERIOD          => 50.0,
      CLKOUT_PHASE_SHIFT    => "NONE",
      DCM_AUTOCALIBRATION   => TRUE,
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
      DFS_FREQUENCY_MODE    => "LOW",
      DLL_FREQUENCY_MODE    => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF            => x"F0F0",
      PHASE_SHIFT           => 0,
      STARTUP_WAIT          => FALSE )
    port map (
      CLKIN    => CLK_IN,
      CLKFB    => GND,
      DADDR    => GND_BUS(6 downto 0),
      DCLK     => GND,
      DEN      => GND,
      DI       => GND_BUS,
      DWE      => GND,
      PSCLK    => GND,
      PSEN     => GND,
      PSINCDEC => GND,
      RST      => RST,
      CLKDV    => open,
      CLKFX    => CLKFX_int,
      CLKFX180 => open,
      CLK0     => open,
      CLK2X    => open,
      CLK2X180 => open,
      CLK90    => open,
      CLK180   => open,
      CLK270   => open,
      DO       => open,
      DRDY     => open,
      LOCKED   => LOCK,
      PSDONE   => open );

  iBUFG1 : BUFG port map (I=>CLKFX_int, O=>CLKFX_buf);

  CLKFX <= CLKFX_buf;

end LF_DFS_SUBM_arch;
