# ============================================
#  Synthesis script - Leonardo Spectrum
# ============================================
#  Example 1 / HERON-FPGA14
# ============================================

puts ""
puts " Synthesis script for HERON-FPGA14 Example 1"
puts ""

# Global timing constraints (100 MHz)
set input2register 10.0
set register2output 10.0
set register2register 10.0

#Technology settings and then load library
set part 4vsx35ff668
set process 11
set wire_table xc4vsx-35-11_wc
load_library xc4v

#Read in the design
read { ../../Common/HE_RWCLK.vhd
       ../../Common/HE_WR_6F.vhd
       ../../Common/HE_RD_6F.vhd
       ../../Common/HE_MSG_MSTR.vhd
       ../../Common/HE_USER.vhd
       ../../Common/HE_DDR_DATA.vhd
       ../../Common/HE_DDR_CTRL.vhd
       ../../Common/HE_DDR.vhd
       ../Src/HSB1.vhd
       ../Src/USER_AP1.vhd
       ../../Common/TOP.vhd }

#Optimize the design and apply timing
optimize -target xc4v -chip -area -effort quick -hierarchy auto 
optimize_timing

#Write out the edf netlist for PnR
auto_write Ex1_top.edf
