-- ==============================================================
-- FILE : HE_RWCLK.VHD  -  DO NOT EDIT THIS FILE
-- ==============================================================
--
-- This file is part of the Hardware Interface Layer (H.I.L) of
-- your project when using your HERON-FPGA14 module.
--
-- This file must NOT be modified by users of the Module.
--
-- ==============================================================
--
--  Module      : HE_RWCLK
--  Date        : 28/02/2002
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : FIFO Clock, same for the IN and OUT FIFOs
--
-- ==============================================================
--
--  Notes :
--  -1-  Using CLKDLL primitives (inspite of DCM for Virtex2)
--       for source code compatibilty with Spartan2.
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    28-02-02    First Written
--  1.1     R. Williams    08-05-02    Syntax change made to all
--                                     instanciated components,
--                                     (changed '0' to GND)
--                                     for compatibility with
--                                     ModelSim5.5b.
--  1.2     R. Williams    11-06-02    Added 1ns delay on paths
--                                     from inferred flip-flops
--                                     to instantiated flip-flops
--                                     to prevent setup violations
--                                     in functional simulation.
--  2.0     R. Williams    10-10-02    New components added for
--                                     interfacing to all six HERON
--                                     input FIFOs and all six HERON
--                                     output FIFOs at the same time.
--                                     Added component HE_RD_6F in
--                                     place of component HE_RD_1F.
--                                     Added component HE_WR_6F in
--                                     place of component HE_WR_1F.
--  2.1     R. Williams    20-01-03    Changes made to the HSB
--                                     mastering functions, and 
--                                     additional registering added
--                                     to the AE flag to ensure
--                                     correct reading from HEPC8s.
--
-- ==============================================================


library IEEE;
  use IEEE.std_logic_1164.all;

-- synopsys translate_off
library UNISIM;
  use UNISIM.vcomponents.all;
-- synopsys translate_on

entity HE_RWCLK is
  port (
    -- External PADS
    DCLK : in  std_logic;
    FCLK : out std_logic;
    -- Module I/Os
    RST  : in  std_logic;
    CLK  : in  std_logic;
    GCLK : out std_logic
  );
end HE_RWCLK;


architecture RTL of HE_RWCLK is

  component DCM_ADV
    generic (
      CLK_FEEDBACK          : string :=  "1X";
      CLKDV_DIVIDE          : real :=  2.000000;
      CLKFX_DIVIDE          : integer :=  1;
      CLKFX_MULTIPLY        : integer :=  4;
      CLKIN_DIVIDE_BY_2     : boolean :=  FALSE;
      CLKIN_PERIOD          : real :=  0.000000;
      CLKOUT_PHASE_SHIFT    : string :=  "NONE";
      DCM_AUTOCALIBRATION   : boolean :=  TRUE;
      DCM_PERFORMANCE_MODE  : string :=  "MAX_SPEED";
      DESKEW_ADJUST         : string :=  "SYSTEM_SYNCHRONOUS";
      DFS_FREQUENCY_MODE    : string :=  "LOW";
      DLL_FREQUENCY_MODE    : string :=  "LOW";
      DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
      PHASE_SHIFT           : integer :=  0;
      STARTUP_WAIT          : boolean :=  FALSE;
      FACTORY_JF            : bit_vector :=  x"F0F0"
    );
    port (
      CLKIN    : in  std_logic;
      CLKFB    : in  std_logic;
      DADDR    : in  std_logic_vector(6 downto 0);
      DI       : in  std_logic_vector(15 downto 0);
      DWE      : in  std_logic;
      DEN      : in  std_logic;
      DCLK     : in  std_logic;
      RST      : in  std_logic;
      PSEN     : in  std_logic;
      PSINCDEC : in  std_logic;
      PSCLK    : in  std_logic;
      CLK0     : out std_logic;
      CLK90    : out std_logic;
      CLK180   : out std_logic;
      CLK270   : out std_logic;
      CLKDV    : out std_logic;
      CLK2X    : out std_logic;
      CLK2X180 : out std_logic;
      CLKFX    : out std_logic;
      CLKFX180 : out std_logic;
      DRDY     : out std_logic;
      DO       : out std_logic_vector(15 downto 0);
      LOCKED   : out std_logic;
      PSDONE   : out std_logic
    );
  end component;

  component CLKDLLHF
    port (CLKIN  : in  std_logic;
          CLKFB  : in  std_logic;
          RST    : in  std_logic;
          CLK0   : out std_logic;
          CLK180 : out std_logic;
          CLKDV  : out std_logic;
          LOCKED : out std_logic);
  end component;

  component BUFG
    port(I : in  std_logic;
         O : out std_logic);
  end component;

  component FDP
    port(
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      PRE : in  std_logic);
  end component;

--signal GND     : std_logic;
  signal R1      : std_logic;
  signal R2      : std_logic;
  signal RST_DLL : std_logic;
  signal CLKIN   : std_logic;
  signal CLK0    : std_logic;
  signal GCLK0   : std_logic;

   signal GND        : std_logic_vector (6 downto 0);
   signal GND1       : std_logic_vector (15 downto 0);
   signal GND2       : std_logic;

begin

  FCLK <= CLK;    -- OBUF_F_24 (instanciation in the top level)

  CLKIN <= DCLK;  -- IBUFG (instanciation in the top level)


    process(CLK)
    begin
      if rising_edge(CLK) then
        RST_DLL <= R2 AND (NOT R1);
      end if;
    end process;

    iFDP0: FDP
      port map ( Q   => R1,
                 D   => RST,
                 C   => CLK,
                 PRE => GND2 );

    iFDP1: FDP
      port map ( Q    => R2,
                 D    => R1,
                 C    => CLK,
                 PRE  => GND2 );

--  iDLL : CLKDLLHF
--    port map ( CLKIN => CLKIN,
--               CLKFB => GCLK0,
--               RST   => RST_DLL,
--               CLK0  => CLK0 );

   GND(6 downto 0) <= "0000000";
   GND1(15 downto 0) <= "0000000000000000";
   GND2 <= '0';

    DCM_ADV_INST : DCM_ADV
      generic map (
        CLK_FEEDBACK => "1X",
        CLKDV_DIVIDE => 2.000000,
        CLKFX_DIVIDE => 1,
        CLKFX_MULTIPLY => 4,
        CLKIN_DIVIDE_BY_2 => FALSE,
        CLKIN_PERIOD => 10.000000,
        CLKOUT_PHASE_SHIFT => "NONE",
        DCM_AUTOCALIBRATION => TRUE,
        DCM_PERFORMANCE_MODE => "MAX_SPEED",
        DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
        DFS_FREQUENCY_MODE => "LOW",
        DLL_FREQUENCY_MODE => "LOW",
        DUTY_CYCLE_CORRECTION => TRUE,
        PHASE_SHIFT => 0,
        STARTUP_WAIT => FALSE,
        FACTORY_JF => x"F0F0" )
      port map (
        CLKFB=>GCLK0,
        CLKIN=>CLKIN,
        DADDR(6 downto 0)=>GND(6 downto 0),
        DCLK=>GND2,
        DEN=>GND2,
        DI(15 downto 0)=>GND1(15 downto 0),
        DWE=>GND2,
        PSCLK=>GND2,
        PSEN=>GND2,
        PSINCDEC=>GND2,
        RST=>RST_DLL,
        CLKDV=>open,
        CLKFX=>open,
        CLKFX180=>open,
        CLK0=>CLK0,
        CLK2X=>open,
        CLK2X180=>open,
        CLK90=>open,
        CLK180=>open,
        CLK270=>open,
        DO=>open,
        DRDY=>open,
        LOCKED=>open,
        PSDONE=>open );

  bGCK : BUFG port map (I=>CLK0, O=>GCLK0);
  GCLK <= GCLK0;

end RTL;

