-- ==============================================================
-- FILE : DFS_DCM.VHD  -  may be modified by the USER
-- ==============================================================
--
-- This file is part of Example 3, for the HERON-FPGA14 module.
--
-- This file may be modified by the user.
--
-- ==============================================================
--
--  Module      : DFS_DCM
--  Date        : 06/04/2006
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : DCM used to generate 200MHz from 100MHz
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    06-04-06    Taken from FPGA12 Example 3.
--
-- ==============================================================



library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.vcomponents.all;
-- pragma translate_on


entity DFS_DCM is
  port (
    CLKIN_IN   : in  std_logic;
    RST_IN     : in  std_logic;
    CLKFX_OUT  : out std_logic;
    CLK0_OUT   : out std_logic;
    LOCKED_OUT : out std_logic
  );
end DFS_DCM;


architecture STRUCT of DFS_DCM is

  component BUFG
    port (
      I : in  std_logic;
      O : out std_logic
    );
  end component;

  -- Period Jitter (unit interval) for block DCM_INST = 0.11 UI
  -- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.70 ns
  component DCM
    generic(
      CLK_FEEDBACK          : string :=  "1X";
      CLKDV_DIVIDE          : real :=  2.000000;
      CLKFX_DIVIDE          : integer :=  1;
      CLKFX_MULTIPLY        : integer :=  4;
      CLKIN_DIVIDE_BY_2     : boolean :=  FALSE;
      CLKIN_PERIOD          : real :=  0.000000;
      CLKOUT_PHASE_SHIFT    : string :=  "NONE";
      DESKEW_ADJUST         : string :=  "SYSTEM_SYNCHRONOUS";
      DFS_FREQUENCY_MODE    : string :=  "LOW";
      DLL_FREQUENCY_MODE    : string :=  "LOW";
      DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
      FACTORY_JF            : bit_vector :=  x"C080";
      PHASE_SHIFT           : integer :=  0;
      STARTUP_WAIT          : boolean :=  FALSE;
      DSS_MODE              : string :=  "NONE"
    );
    port (
      CLKIN    : in  std_logic;
      CLKFB    : in  std_logic;
      RST      : in  std_logic;
      PSEN     : in  std_logic;
      PSINCDEC : in  std_logic;
      PSCLK    : in  std_logic;
      DSSEN    : in  std_logic;
      CLK0     : out std_logic;
      CLK90    : out std_logic;
      CLK180   : out std_logic;
      CLK270   : out std_logic;
      CLKDV    : out std_logic;
      CLK2X    : out std_logic;
      CLK2X180 : out std_logic;
      CLKFX    : out std_logic;
      CLKFX180 : out std_logic;
      STATUS   : out std_logic_vector(7 downto 0);
      LOCKED   : out std_logic;
      PSDONE   : out std_logic
    );
  end component;

  signal CLKFB_IN  : std_logic;
  signal CLKFX_BUF : std_logic;
  signal CLK0_BUF  : std_logic;
  signal GND       : std_logic;

begin

  GND <= '0';

  CLK0_OUT <= CLKFB_IN;

  CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT);

  CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN);

  DCM_INST : DCM
    generic map (
      CLK_FEEDBACK          => "1X",
      CLKDV_DIVIDE          => 2.000000,
      CLKFX_DIVIDE          => 1,
      CLKFX_MULTIPLY        => 2,
      CLKIN_DIVIDE_BY_2     => FALSE,
      CLKIN_PERIOD          => 10.000000,
      CLKOUT_PHASE_SHIFT    => "NONE",
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
      DFS_FREQUENCY_MODE    => "LOW",
      DLL_FREQUENCY_MODE    => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      FACTORY_JF            => x"C080",
      PHASE_SHIFT           => 0,
      STARTUP_WAIT          => FALSE )
    port map (
      CLKFB    => CLKFB_IN,
      CLKIN    => CLKIN_IN,
      DSSEN    => GND,
      PSCLK    => GND,
      PSEN     => GND,
      PSINCDEC => GND,
      RST      => RST_IN,
      CLKDV    => open,
      CLKFX    => CLKFX_BUF,
      CLKFX180 => open,
      CLK0     => CLK0_BUF,
      CLK2X    => open,
      CLK2X180 => open,
      CLK90    => open,
      CLK180   => open,
      CLK270   => open,
      LOCKED   => LOCKED_OUT,
      PSDONE   => open,
      STATUS   => open );

end STRUCT;
