-- ==============================================================
-- FILE : HE_DDR_DATA.VHD  -  DO NOT EDIT THIS FILE
-- ==============================================================
--
-- This file is part of the Hardware Interface Layer (H.I.L) of
-- your project when using your HERON-FPGA14 module.
--
-- This file must NOT be modified by users of the Module.
--
-- ==============================================================
--
--  Module      : HE_DDR_DATA
--  Date        : 01/07/2004
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : DDR SDRAM Interface Data Path
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    01-07-04    First Written
--  1.1     R. Williams    01-08-05    Changed use of 'rdrise_ef'
--                                     to 'rdrise_af' and changed
--                                     'rdfall_ef' to 'rdfall_af'
--                                     for read address fifo read
--                                     enable logic. This was done
--                                     to improve DDR read speeds.
--  2.0     R. Williams    01-12-05    Re-designed for the
--                                     Virtex-4.
--  2.1     R. Williams    07-04-06    Increased DDR start-delay
--                                     from 200us to 300us and
--                                     changed use of LOCKED signal
--                                     to prevent failure of MRS
--                                     commands on start-up.
--                                     Forced output data-enable
--                                     to IOBs.
--  2.2     R. Williams    04-07-06    Redesigned to use a DCM
--                                     output for the Write-Clock.
--                                     This gives better timing
--                                     performance by using
--                                     duty cycle correction to
--                                     improve the mark-space
--                                     ratio of the input clock.
--  2.3     R. Williams    27-09-07    Change made to control
--                                     logic to ensure write has
--                                     priority over read while
--                                     both ready in the same row.
--  3.0     R. Williams    07-04-08    DDR Interface re-designed
--                                     to increase control signal
--                                     margins w.r.t ddr_clk.
--
-- ==============================================================



-- ==============================================================
--  Module      : HE_DDR_A_DATA
--  Description : DDR Port A Data

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;


-- pragma translate_off
library UNISIM;
  use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity HE_DDR_A_DATA is
  port(
    user_input_data   : in  std_logic_vector(71 downto 0);
    clk90             : in  std_logic;
    clk180            : in  std_logic;
    clk270            : in  std_logic;
    reset             : in  std_logic;
    DQS_enable        : in  std_logic;
    DQS_reset         : in  std_logic;
    write_enable      : in  std_logic;
    read_enable       : in  std_logic;
    read_select       : in  std_logic;
    wclk              : in  std_logic;
    ddr_dq_in         : in  std_logic_vector(31 downto 0);
    ddr_dq_out        : out std_logic_vector(31 downto 0);
    ddr_dq_en         : out std_logic_vector(31 downto 0);
    ddr_dqs_in        : in  std_logic_vector(3 downto 0);
    ddr_dqs_out       : out std_logic_vector(3 downto 0);
    ddr_dqs_en        : out std_logic_vector(3 downto 0);
    ddr_dm_out        : out std_logic_vector(3 downto 0);
    ddr_dm_en         : out std_logic_vector(3 downto 0);
    read_data_rising  : out std_logic_vector(31 downto 0);
    read_data_falling : out std_logic_vector(31 downto 0);
    control_a1        : out std_logic;
    control_a2        : out std_logic;
    control_ab1       : out std_logic;
    control_ab2       : out std_logic
  );
end HE_DDR_A_DATA;

architecture RTL of HE_DDR_A_DATA is

  component IDELAYCTRL
    port(
      RDY    : out std_ulogic;
      REFCLK : in  std_ulogic;
      RST    : in  std_ulogic
    );
  end component;

  component FDC
    port (
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CLR : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  component HE_DDR_A_IOB_A
    port (
      reset              : in  std_logic;
      clk180             : in  std_logic;
      wclk               : in  std_logic;
      dqs                : in  std_logic;
      write_en_val       : in  std_logic;
      read_en_val        : in  std_logic;
      write_data_rising  : in  std_logic_vector(7 downto 0);
      write_data_falling : in  std_logic_vector(7 downto 0);
      read_data_rising   : out std_logic_vector(7 downto 0);
      read_data_falling  : out std_logic_vector(7 downto 0);
      ddr_data_in        : in  std_logic_vector(7 downto 0);
      ddr_data_out       : out std_logic_vector(7 downto 0);
      ddr_data_en        : out std_logic_vector(7 downto 0)
    );
  end component;

  component HE_DDR_A_IOB_B
    port (
      reset              : in  std_logic;
      clk180             : in  std_logic;
      wclk               : in  std_logic;
      dqs                : in  std_logic;
      write_en_val       : in  std_logic;
      read_en_val        : in  std_logic;
      write_data_rising  : in  std_logic_vector(7 downto 0);
      write_data_falling : in  std_logic_vector(7 downto 0);
      read_data_rising   : out std_logic_vector(7 downto 0);
      read_data_falling  : out std_logic_vector(7 downto 0);
      ddr_data_in        : in  std_logic_vector(7 downto 0);
      ddr_data_out       : out std_logic_vector(7 downto 0);
      ddr_data_en        : out std_logic_vector(7 downto 0)
    );
  end component;

  component HE_DDR_A_IOB_C
    port (
      reset              : in  std_logic;
      clk180             : in  std_logic;
      wclk               : in  std_logic;
      dqs                : in  std_logic;
      write_en_val       : in  std_logic;
      read_en_val        : in  std_logic;
      write_data_rising  : in  std_logic_vector(7 downto 0);
      write_data_falling : in  std_logic_vector(7 downto 0);
      read_data_rising   : out std_logic_vector(7 downto 0);
      read_data_falling  : out std_logic_vector(7 downto 0);
      ddr_data_in        : in  std_logic_vector(7 downto 0);
      ddr_data_out       : out std_logic_vector(7 downto 0);
      ddr_data_en        : out std_logic_vector(7 downto 0)
    );
  end component;

  component HE_DDR_A_IOB_D
    port (
      reset              : in  std_logic;
      clk180             : in  std_logic;
      wclk               : in  std_logic;
      dqs                : in  std_logic;
      write_en_val       : in  std_logic;
      read_en_val        : in  std_logic;
      write_data_rising  : in  std_logic_vector(7 downto 0);
      write_data_falling : in  std_logic_vector(7 downto 0);
      read_data_rising   : out std_logic_vector(7 downto 0);
      read_data_falling  : out std_logic_vector(7 downto 0);
      ddr_data_in        : in  std_logic_vector(7 downto 0);
      ddr_data_out       : out std_logic_vector(7 downto 0);
      ddr_data_en        : out std_logic_vector(7 downto 0)
    );
  end component;

  component HE_DDR_DQS
    port (
      DQS_enable  : in  std_logic;
      DQS_reset   : in  std_logic;
      clk         : in  std_logic;
      clk180      : in  std_logic;
      DDR_DQS_IN  : in  std_logic_vector(3 downto 0);
      DDR_DQS_OUT : out std_logic_vector(3 downto 0);
      DDR_DQS_EN  : out std_logic_vector(3 downto 0);
      DQS         : out std_logic_vector(3 downto 0)
    );
  end component;

  component HE_DDR_DM_IOB
    port (
      write_data_mask_rising  : in  std_logic;
      write_data_mask_falling : in  std_logic;
      wclk                    : in  std_logic;
      reset                   : in  std_logic;
      write_en_val            : in  std_logic;
      ddr_dm_out              : out std_logic;
      ddr_dm_en               : out std_logic
    );
  end component;

  attribute LOC : string;

  attribute LOC of iIDELAYCTRL0 : label is "IDELAYCTRL_X2Y0";
  attribute LOC of iIDELAYCTRL1 : label is "IDELAYCTRL_X2Y1";

  signal VCC                     : std_logic;
  signal wclkb                   : std_logic;

  signal dqs                     : std_logic_vector(3 downto 0);

  signal write_data_rising       : std_logic_vector(31 downto 0);
  signal write_data_falling      : std_logic_vector(31 downto 0);
  signal write_data_mask_rising  : std_logic_vector(3 downto 0);
  signal write_data_mask_falling : std_logic_vector(3 downto 0);
  signal write_en_val            : std_logic_vector(3 downto 0);

  signal temp_data_falling       : std_logic_vector(31 downto 0);
  signal temp_data_mask_falling  : std_logic_vector(3 downto 0);

  signal read_en_P4              : std_logic;
  signal read_en_P5              : std_logic;
  signal read_en_val             : std_logic;

  signal read_sel_P4             : std_logic;
  signal read_sel_P5             : std_logic;
  signal read_sel_val            : std_logic;

  signal read_en_val_fn          : std_logic;
  signal read_en_val_a           : std_logic;
  signal read_en_val_b           : std_logic;
  signal read_en_val_c           : std_logic;
  signal read_en_val_d           : std_logic;

begin

  VCC <= '1';

  wclkb <= not wclk;

  iIDELAYCTRL0 : IDELAYCTRL
    port map (
      RDY    => open,
      REFCLK => clk90,
      RST    => reset );

  iIDELAYCTRL1 : IDELAYCTRL
    port map (
      RDY    => open,
      REFCLK => clk90,
      RST    => reset );

  process(reset, clk90)
  begin
    if reset='1' then
      write_data_rising <= (others=>'0');
      temp_data_falling <= (others=>'0');
    elsif clk90'event and clk90='1' then
      write_data_rising <= user_input_data(39 downto 8);
      temp_data_falling <= user_input_data(71 downto 40);
    end if;
  end process;

  process(reset, wclk)
  begin
    if reset='1' then
      write_data_falling <= (others=>'0');
    elsif wclk'event and wclk='1' then
      write_data_falling <= temp_data_falling;
    end if;
  end process;

  process(reset, clk90)
  begin
    if reset='1' then
      write_data_mask_rising <= (others=>'0');
      temp_data_mask_falling <= (others=>'0');
    elsif clk90'event and clk90='1' then
      write_data_mask_rising <= user_input_data(7 downto 4);
      temp_data_mask_falling <= user_input_data(3 downto 0);
    end if;
  end process;

  process(reset, wclk)
  begin
    if reset='1' then
      write_data_mask_falling <= (others=>'0');
    elsif wclk'event and wclk='1' then
      write_data_mask_falling <= temp_data_mask_falling;
    end if;
  end process;

  iWEV0 : FDCE port map (D=>write_enable, CLR=>reset, C=>clk90, Q=>write_en_val(0), CE=>VCC);
  iWEV1 : FDCE port map (D=>write_enable, CLR=>reset, C=>clk90, Q=>write_en_val(1), CE=>VCC);
  iWEV2 : FDCE port map (D=>write_enable, CLR=>reset, C=>clk90, Q=>write_en_val(2), CE=>VCC);
  iWEV3 : FDCE port map (D=>write_enable, CLR=>reset, C=>clk90, Q=>write_en_val(3), CE=>VCC);

  process(reset, clk180)
  begin
    if reset='1' then
      read_en_P4  <= '0';
      read_en_P5  <= '0';
      read_en_val <= '0';
    elsif clk180'event and clk180='1' then
      read_en_P4  <= read_enable;
      read_en_P5  <= read_en_P4;
      read_en_val <= read_en_P5;
    end if;
  end process;

  process(reset, clk180)
  begin
    if reset='1' then
      read_sel_P4  <= '0';
      read_sel_P5  <= '0';
      read_sel_val <= '0';
    elsif clk180'event and clk180='1' then
      read_sel_P4  <= read_select;
      read_sel_P5  <= read_sel_P4;
      read_sel_val <= read_sel_P5;
    end if;
  end process;

  read_en_val_fn <= read_en_P4 OR read_en_P5;

  iRD_EN_A : FDC port map (Q=>read_en_val_a, D=>read_en_val_fn, C=>clk180, CLR=>reset);
  iRD_EN_B : FDC port map (Q=>read_en_val_b, D=>read_en_val_fn, C=>clk180, CLR=>reset);
  iRD_EN_C : FDC port map (Q=>read_en_val_c, D=>read_en_val_fn, C=>clk180, CLR=>reset);
  iRD_EN_D : FDC port map (Q=>read_en_val_d, D=>read_en_val_fn, C=>clk180, CLR=>reset);

  process(reset, clk180)
  begin
    if reset='1' then
      control_a1  <= '0';
      control_a2  <= '0';
      control_ab1 <= '0';
      control_ab2 <= '0';
    elsif clk180'event and clk180='1' then
      control_a1 <= '0';
      control_a2 <= '0';
      if (read_en_val='1' and read_sel_val='0') then
        control_a1 <= '1';
      end if;
      if (read_en_val='1' and read_sel_val='1') then
        control_a2 <= '1';
      end if;
      control_ab1 <= '0';
      control_ab2 <= '0';
      if (read_en_val='1' and read_sel_val='0') then
        control_ab1 <= '1';
      end if;
      if (read_en_val='1' and read_sel_val='1') then
        control_ab2 <= '1';
      end if;
    end if;
  end process;

  U_BYTE0 : HE_DDR_A_IOB_A
    port map (
      reset              => reset,
      clk180             => clk180,
      wclk               => wclk,
      dqs                => dqs(0),
      write_en_val       => write_en_val(0),
      read_en_val        => read_en_val_a,
      write_data_rising  => write_data_rising(7 downto 0),
      write_data_falling => write_data_falling(7 downto 0),
      read_data_rising   => read_data_rising(7 downto 0),
      read_data_falling  => read_data_falling(7 downto 0),
      ddr_data_in        => ddr_dq_in(7 downto 0),
      ddr_data_out       => ddr_dq_out(7 downto 0),
      ddr_data_en        => ddr_dq_en(7 downto 0) );

  U_BYTE1 : HE_DDR_A_IOB_B
    port map (
      reset              => reset,
      clk180             => clk180,
      wclk               => wclk,
      dqs                => dqs(1),
      write_en_val       => write_en_val(1),
      read_en_val        => read_en_val_b,
      write_data_rising  => write_data_rising(15 downto 8),
      write_data_falling => write_data_falling(15 downto 8),
      read_data_rising   => read_data_rising(15 downto 8),
      read_data_falling  => read_data_falling(15 downto 8),
      ddr_data_in        => ddr_dq_in(15 downto 8),
      ddr_data_out       => ddr_dq_out(15 downto 8),
      ddr_data_en        => ddr_dq_en(15 downto 8) );

  U_BYTE2 : HE_DDR_A_IOB_C
    port map (
      reset              => reset,
      clk180             => clk180,
      wclk               => wclk,
      dqs                => dqs(2),
      write_en_val       => write_en_val(2),
      read_en_val        => read_en_val_c,
      write_data_rising  => write_data_rising(23 downto 16),
      write_data_falling => write_data_falling(23 downto 16),
      read_data_rising   => read_data_rising(23 downto 16),
      read_data_falling  => read_data_falling(23 downto 16),
      ddr_data_in        => ddr_dq_in(23 downto 16),
      ddr_data_out       => ddr_dq_out(23 downto 16),
      ddr_data_en        => ddr_dq_en(23 downto 16) );

  U_BYTE3 : HE_DDR_A_IOB_D
    port map (
      reset              => reset,
      clk180             => clk180,
      wclk               => wclk,
      dqs                => dqs(3),
      write_en_val       => write_en_val(3),
      read_en_val        => read_en_val_d,
      write_data_rising  => write_data_rising(31 downto 24),
      write_data_falling => write_data_falling(31 downto 24),
      read_data_rising   => read_data_rising(31 downto 24),
      read_data_falling  => read_data_falling(31 downto 24),
      ddr_data_in        => ddr_dq_in(31 downto 24),
      ddr_data_out       => ddr_dq_out(31 downto 24),
      ddr_data_en        => ddr_dq_en(31 downto 24) );

  INST_2 : HE_DDR_DQS
    port map (
      DQS_enable  => DQS_enable,
      DQS_reset   => DQS_reset,
      clk         => clk90,
      clk180      => clk270,
      DDR_DQS_IN  => ddr_dqs_in,
      DDR_DQS_OUT => ddr_dqs_out,
      DDR_DQS_EN  => ddr_dqs_en,
      DQS         => dqs );

  U_DMASK_byte0 : HE_DDR_DM_IOB
    port map (
      write_data_mask_rising  => write_data_mask_rising(0),
      write_data_mask_falling => write_data_mask_falling(0),
      wclk                    => wclk,
      reset                   => reset,
      write_en_val            => write_en_val(0),
      ddr_dm_out              => ddr_dm_out(0),
      ddr_dm_en               => ddr_dm_en(0) );

  U_DMASK_byte1 : HE_DDR_DM_IOB
    port map (
      write_data_mask_rising  => write_data_mask_rising(1),
      write_data_mask_falling => write_data_mask_falling(1),
      wclk                    => wclk,
      reset                   => reset,
      write_en_val            => write_en_val(1),
      ddr_dm_out              => ddr_dm_out(1),
      ddr_dm_en               => ddr_dm_en(1) );

  U_DMASK_byte2 : HE_DDR_DM_IOB
    port map (
      write_data_mask_rising  => write_data_mask_rising(2),
      write_data_mask_falling => write_data_mask_falling(2),
      wclk                    => wclk,
      reset                   => reset,
      write_en_val            => write_en_val(2),
      ddr_dm_out              => ddr_dm_out(2),
      ddr_dm_en               => ddr_dm_en(2) );

  U_DMASK_byte3 : HE_DDR_DM_IOB
    port map (
      write_data_mask_rising  => write_data_mask_rising(3),
      write_data_mask_falling => write_data_mask_falling(3),
      wclk                    => wclk,
      reset                   => reset,
      write_en_val            => write_en_val(3),
      ddr_dm_out              => ddr_dm_out(3),
      ddr_dm_en               => ddr_dm_en(3) );

end RTL;


-- ==============================================================
--  Module      : HE_DDR_A_IOB_A
--  Description : DDR Port A Data, Byte 0

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;


-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity HE_DDR_A_IOB_A is
  port (
    reset              : in  std_logic;
    clk180             : in  std_logic;
    wclk               : in  std_logic;
    dqs                : in  std_logic;
    write_en_val       : in  std_logic;
    read_en_val        : in  std_logic;
    write_data_rising  : in  std_logic_vector(7 downto 0);
    write_data_falling : in  std_logic_vector(7 downto 0);
    read_data_rising   : out std_logic_vector(7 downto 0);
    read_data_falling  : out std_logic_vector(7 downto 0);
    ddr_data_in        : in  std_logic_vector(7 downto 0);
    ddr_data_out       : out std_logic_vector(7 downto 0);
    ddr_data_en        : out std_logic_vector(7 downto 0)
  );
end HE_DDR_A_IOB_A;


architecture RTL of HE_DDR_A_IOB_A is

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FDDRRSE
    port (
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  attribute IOB            : string;
  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute DDR_CLK_EDGE   : string;
  attribute SRTYPE         : string;

  attribute IOB of iOEN_0  : label is "TRUE";
  attribute IOB of iOEN_1  : label is "TRUE";
  attribute IOB of iOEN_2  : label is "TRUE";
  attribute IOB of iOEN_3  : label is "TRUE";
  attribute IOB of iOEN_4  : label is "TRUE";
  attribute IOB of iOEN_5  : label is "TRUE";
  attribute IOB of iOEN_6  : label is "TRUE";
  attribute IOB of iOEN_7  : label is "TRUE";

  attribute IOBDELAY_TYPE  of iIDD_0 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_1 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_2 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_3 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_4 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_5 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_6 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_7 : label is "FIXED";

  attribute IOBDELAY_VALUE of iIDD_0 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_1 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_2 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_3 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_4 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_5 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_6 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_7 : label is 12;

  attribute DDR_CLK_EDGE of iIFD_0 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_1 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_2 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_3 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_4 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_5 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_6 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_7 : label is "SAME_EDGE_PIPELINED";

  attribute SRTYPE of iIFD_0 : label is "SYNC";
  attribute SRTYPE of iIFD_1 : label is "SYNC";
  attribute SRTYPE of iIFD_2 : label is "SYNC";
  attribute SRTYPE of iIFD_3 : label is "SYNC";
  attribute SRTYPE of iIFD_4 : label is "SYNC";
  attribute SRTYPE of iIFD_5 : label is "SYNC";
  attribute SRTYPE of iIFD_6 : label is "SYNC";
  attribute SRTYPE of iIFD_7 : label is "SYNC";

  signal GND          : std_logic;
  signal VCC          : std_logic;

  signal wclkb        : std_logic;
  signal delayed_data : std_logic_vector(7 downto 0);

begin

  GND <= '0';
  VCC <= '1';

  wclkb <= not wclk;

  iOFD_0 : FDDRRSE port map (Q=>ddr_data_out(0), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(0), D1=>write_data_falling(0), R=>GND, S=>GND);
  iOFD_1 : FDDRRSE port map (Q=>ddr_data_out(1), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(1), D1=>write_data_falling(1), R=>GND, S=>GND);
  iOFD_2 : FDDRRSE port map (Q=>ddr_data_out(2), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(2), D1=>write_data_falling(2), R=>GND, S=>GND);
  iOFD_3 : FDDRRSE port map (Q=>ddr_data_out(3), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(3), D1=>write_data_falling(3), R=>GND, S=>GND);
  iOFD_4 : FDDRRSE port map (Q=>ddr_data_out(4), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(4), D1=>write_data_falling(4), R=>GND, S=>GND);
  iOFD_5 : FDDRRSE port map (Q=>ddr_data_out(5), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(5), D1=>write_data_falling(5), R=>GND, S=>GND);
  iOFD_6 : FDDRRSE port map (Q=>ddr_data_out(6), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(6), D1=>write_data_falling(6), R=>GND, S=>GND);
  iOFD_7 : FDDRRSE port map (Q=>ddr_data_out(7), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(7), D1=>write_data_falling(7), R=>GND, S=>GND);

  iOEN_0 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(0), CE=>VCC);
  iOEN_1 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(1), CE=>VCC);
  iOEN_2 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(2), CE=>VCC);
  iOEN_3 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(3), CE=>VCC);
  iOEN_4 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(4), CE=>VCC);
  iOEN_5 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(5), CE=>VCC);
  iOEN_6 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(6), CE=>VCC);
  iOEN_7 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(7), CE=>VCC);

  iIDD_0 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(0),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(0),
      INC => GND,
      RST => GND );

  iIDD_1 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(1),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(1),
      INC => GND,
      RST => GND );

  iIDD_2 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(2),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(2),
      INC => GND,
      RST => GND );

  iIDD_3 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(3),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(3),
      INC => GND,
      RST => GND );

  iIDD_4 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(4),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(4),
      INC => GND,
      RST => GND );

  iIDD_5 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(5),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(5),
      INC => GND,
      RST => GND );

  iIDD_6 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(6),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(6),
      INC => GND,
      RST => GND );

  iIDD_7 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(7),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(7),
      INC => GND,
      RST => GND );

  iIFD_0 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(0),
      Q2 => read_data_falling(0),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(0),
      R  => GND,
      S  => GND );

  iIFD_1 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(1),
      Q2 => read_data_falling(1),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(1),
      R  => GND,
      S  => GND );

  iIFD_2 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(2),
      Q2 => read_data_falling(2),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(2),
      R  => GND,
      S  => GND );

  iIFD_3 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(3),
      Q2 => read_data_falling(3),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(3),
      R  => GND,
      S  => GND );

  iIFD_4 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(4),
      Q2 => read_data_falling(4),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(4),
      R  => GND,
      S  => GND );

  iIFD_5 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(5),
      Q2 => read_data_falling(5),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(5),
      R  => GND,
      S  => GND );

  iIFD_6 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(6),
      Q2 => read_data_falling(6),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(6),
      R  => GND,
      S  => GND );

  iIFD_7 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(7),
      Q2 => read_data_falling(7),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(7),
      R  => GND,
      S  => GND );

end RTL;


-- ==============================================================
--  Module      : HE_DDR_A_IOB_B
--  Description : DDR Port A Data, Byte 1

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;


-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity HE_DDR_A_IOB_B is
  port (
    reset              : in  std_logic;
    clk180             : in  std_logic;
    wclk               : in  std_logic;
    dqs                : in  std_logic;
    write_en_val       : in  std_logic;
    read_en_val        : in  std_logic;
    write_data_rising  : in  std_logic_vector(7 downto 0);
    write_data_falling : in  std_logic_vector(7 downto 0);
    read_data_rising   : out std_logic_vector(7 downto 0);
    read_data_falling  : out std_logic_vector(7 downto 0);
    ddr_data_in        : in  std_logic_vector(7 downto 0);
    ddr_data_out       : out std_logic_vector(7 downto 0);
    ddr_data_en        : out std_logic_vector(7 downto 0)
  );
end HE_DDR_A_IOB_B;


architecture RTL of HE_DDR_A_IOB_B is

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FDDRRSE
    port (
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  attribute IOB            : string;
  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute DDR_CLK_EDGE   : string;
  attribute SRTYPE         : string;

  attribute IOB of iOEN_0  : label is "TRUE";
  attribute IOB of iOEN_1  : label is "TRUE";
  attribute IOB of iOEN_2  : label is "TRUE";
  attribute IOB of iOEN_3  : label is "TRUE";
  attribute IOB of iOEN_4  : label is "TRUE";
  attribute IOB of iOEN_5  : label is "TRUE";
  attribute IOB of iOEN_6  : label is "TRUE";
  attribute IOB of iOEN_7  : label is "TRUE";

  attribute IOBDELAY_TYPE  of iIDD_0 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_1 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_2 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_3 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_4 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_5 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_6 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_7 : label is "FIXED";

  attribute IOBDELAY_VALUE of iIDD_0 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_1 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_2 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_3 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_4 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_5 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_6 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_7 : label is 12;

  attribute DDR_CLK_EDGE of iIFD_0 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_1 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_2 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_3 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_4 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_5 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_6 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_7 : label is "SAME_EDGE_PIPELINED";

  attribute SRTYPE of iIFD_0 : label is "SYNC";
  attribute SRTYPE of iIFD_1 : label is "SYNC";
  attribute SRTYPE of iIFD_2 : label is "SYNC";
  attribute SRTYPE of iIFD_3 : label is "SYNC";
  attribute SRTYPE of iIFD_4 : label is "SYNC";
  attribute SRTYPE of iIFD_5 : label is "SYNC";
  attribute SRTYPE of iIFD_6 : label is "SYNC";
  attribute SRTYPE of iIFD_7 : label is "SYNC";

  signal GND          : std_logic;
  signal VCC          : std_logic;

  signal wclkb        : std_logic;
  signal delayed_data : std_logic_vector(7 downto 0);

begin

  GND <= '0';
  VCC <= '1';

  wclkb <= not wclk;

  iOFD_0 : FDDRRSE port map (Q=>ddr_data_out(0), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(0), D1=>write_data_falling(0), R=>GND, S=>GND);
  iOFD_1 : FDDRRSE port map (Q=>ddr_data_out(1), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(1), D1=>write_data_falling(1), R=>GND, S=>GND);
  iOFD_2 : FDDRRSE port map (Q=>ddr_data_out(2), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(2), D1=>write_data_falling(2), R=>GND, S=>GND);
  iOFD_3 : FDDRRSE port map (Q=>ddr_data_out(3), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(3), D1=>write_data_falling(3), R=>GND, S=>GND);
  iOFD_4 : FDDRRSE port map (Q=>ddr_data_out(4), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(4), D1=>write_data_falling(4), R=>GND, S=>GND);
  iOFD_5 : FDDRRSE port map (Q=>ddr_data_out(5), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(5), D1=>write_data_falling(5), R=>GND, S=>GND);
  iOFD_6 : FDDRRSE port map (Q=>ddr_data_out(6), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(6), D1=>write_data_falling(6), R=>GND, S=>GND);
  iOFD_7 : FDDRRSE port map (Q=>ddr_data_out(7), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(7), D1=>write_data_falling(7), R=>GND, S=>GND);

  iOEN_0 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(0), CE=>VCC);
  iOEN_1 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(1), CE=>VCC);
  iOEN_2 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(2), CE=>VCC);
  iOEN_3 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(3), CE=>VCC);
  iOEN_4 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(4), CE=>VCC);
  iOEN_5 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(5), CE=>VCC);
  iOEN_6 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(6), CE=>VCC);
  iOEN_7 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(7), CE=>VCC);

  iIDD_0 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(0),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(0),
      INC => GND,
      RST => GND );

  iIDD_1 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(1),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(1),
      INC => GND,
      RST => GND );

  iIDD_2 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(2),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(2),
      INC => GND,
      RST => GND );

  iIDD_3 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(3),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(3),
      INC => GND,
      RST => GND );

  iIDD_4 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(4),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(4),
      INC => GND,
      RST => GND );

  iIDD_5 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(5),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(5),
      INC => GND,
      RST => GND );

  iIDD_6 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(6),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(6),
      INC => GND,
      RST => GND );

  iIDD_7 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(7),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(7),
      INC => GND,
      RST => GND );

  iIFD_0 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(0),
      Q2 => read_data_falling(0),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(0),
      R  => GND,
      S  => GND );

  iIFD_1 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(1),
      Q2 => read_data_falling(1),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(1),
      R  => GND,
      S  => GND );

  iIFD_2 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(2),
      Q2 => read_data_falling(2),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(2),
      R  => GND,
      S  => GND );

  iIFD_3 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(3),
      Q2 => read_data_falling(3),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(3),
      R  => GND,
      S  => GND );

  iIFD_4 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(4),
      Q2 => read_data_falling(4),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(4),
      R  => GND,
      S  => GND );

  iIFD_5 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(5),
      Q2 => read_data_falling(5),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(5),
      R  => GND,
      S  => GND );

  iIFD_6 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(6),
      Q2 => read_data_falling(6),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(6),
      R  => GND,
      S  => GND );

  iIFD_7 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(7),
      Q2 => read_data_falling(7),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(7),
      R  => GND,
      S  => GND );

end RTL;


-- ==============================================================
--  Module      : HE_DDR_A_IOB_C
--  Description : DDR Port A Data, Byte 2

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;


-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity HE_DDR_A_IOB_C is
  port (
    reset              : in  std_logic;
    clk180             : in  std_logic;
    wclk               : in  std_logic;
    dqs                : in  std_logic;
    write_en_val       : in  std_logic;
    read_en_val        : in  std_logic;
    write_data_rising  : in  std_logic_vector(7 downto 0);
    write_data_falling : in  std_logic_vector(7 downto 0);
    read_data_rising   : out std_logic_vector(7 downto 0);
    read_data_falling  : out std_logic_vector(7 downto 0);
    ddr_data_in        : in  std_logic_vector(7 downto 0);
    ddr_data_out       : out std_logic_vector(7 downto 0);
    ddr_data_en        : out std_logic_vector(7 downto 0)
  );
end HE_DDR_A_IOB_C;


architecture RTL of HE_DDR_A_IOB_C is

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FDDRRSE
    port (
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  attribute IOB            : string;
  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute DDR_CLK_EDGE   : string;
  attribute SRTYPE         : string;

  attribute IOB of iOEN_0  : label is "TRUE";
  attribute IOB of iOEN_1  : label is "TRUE";
  attribute IOB of iOEN_2  : label is "TRUE";
  attribute IOB of iOEN_3  : label is "TRUE";
  attribute IOB of iOEN_4  : label is "TRUE";
  attribute IOB of iOEN_5  : label is "TRUE";
  attribute IOB of iOEN_6  : label is "TRUE";
  attribute IOB of iOEN_7  : label is "TRUE";

  attribute IOBDELAY_TYPE  of iIDD_0 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_1 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_2 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_3 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_4 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_5 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_6 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_7 : label is "FIXED";

  attribute IOBDELAY_VALUE of iIDD_0 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_1 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_2 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_3 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_4 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_5 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_6 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_7 : label is 12;

  attribute DDR_CLK_EDGE of iIFD_0 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_1 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_2 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_3 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_4 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_5 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_6 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_7 : label is "SAME_EDGE_PIPELINED";

  attribute SRTYPE of iIFD_0 : label is "SYNC";
  attribute SRTYPE of iIFD_1 : label is "SYNC";
  attribute SRTYPE of iIFD_2 : label is "SYNC";
  attribute SRTYPE of iIFD_3 : label is "SYNC";
  attribute SRTYPE of iIFD_4 : label is "SYNC";
  attribute SRTYPE of iIFD_5 : label is "SYNC";
  attribute SRTYPE of iIFD_6 : label is "SYNC";
  attribute SRTYPE of iIFD_7 : label is "SYNC";

  signal GND          : std_logic;
  signal VCC          : std_logic;

  signal wclkb        : std_logic;
  signal delayed_data : std_logic_vector(7 downto 0);

begin

  GND <= '0';
  VCC <= '1';

  wclkb <= not wclk;

  iOFD_0 : FDDRRSE port map (Q=>ddr_data_out(0), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(0), D1=>write_data_falling(0), R=>GND, S=>GND);
  iOFD_1 : FDDRRSE port map (Q=>ddr_data_out(1), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(1), D1=>write_data_falling(1), R=>GND, S=>GND);
  iOFD_2 : FDDRRSE port map (Q=>ddr_data_out(2), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(2), D1=>write_data_falling(2), R=>GND, S=>GND);
  iOFD_3 : FDDRRSE port map (Q=>ddr_data_out(3), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(3), D1=>write_data_falling(3), R=>GND, S=>GND);
  iOFD_4 : FDDRRSE port map (Q=>ddr_data_out(4), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(4), D1=>write_data_falling(4), R=>GND, S=>GND);
  iOFD_5 : FDDRRSE port map (Q=>ddr_data_out(5), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(5), D1=>write_data_falling(5), R=>GND, S=>GND);
  iOFD_6 : FDDRRSE port map (Q=>ddr_data_out(6), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(6), D1=>write_data_falling(6), R=>GND, S=>GND);
  iOFD_7 : FDDRRSE port map (Q=>ddr_data_out(7), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(7), D1=>write_data_falling(7), R=>GND, S=>GND);

  iOEN_0 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(0), CE=>VCC);
  iOEN_1 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(1), CE=>VCC);
  iOEN_2 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(2), CE=>VCC);
  iOEN_3 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(3), CE=>VCC);
  iOEN_4 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(4), CE=>VCC);
  iOEN_5 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(5), CE=>VCC);
  iOEN_6 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(6), CE=>VCC);
  iOEN_7 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(7), CE=>VCC);

  iIDD_0 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(0),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(0),
      INC => GND,
      RST => GND );

  iIDD_1 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(1),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(1),
      INC => GND,
      RST => GND );

  iIDD_2 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(2),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(2),
      INC => GND,
      RST => GND );

  iIDD_3 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(3),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(3),
      INC => GND,
      RST => GND );

  iIDD_4 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(4),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(4),
      INC => GND,
      RST => GND );

  iIDD_5 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(5),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(5),
      INC => GND,
      RST => GND );

  iIDD_6 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(6),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(6),
      INC => GND,
      RST => GND );

  iIDD_7 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(7),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(7),
      INC => GND,
      RST => GND );

  iIFD_0 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(0),
      Q2 => read_data_falling(0),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(0),
      R  => GND,
      S  => GND );

  iIFD_1 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(1),
      Q2 => read_data_falling(1),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(1),
      R  => GND,
      S  => GND );

  iIFD_2 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(2),
      Q2 => read_data_falling(2),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(2),
      R  => GND,
      S  => GND );

  iIFD_3 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(3),
      Q2 => read_data_falling(3),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(3),
      R  => GND,
      S  => GND );

  iIFD_4 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(4),
      Q2 => read_data_falling(4),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(4),
      R  => GND,
      S  => GND );

  iIFD_5 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(5),
      Q2 => read_data_falling(5),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(5),
      R  => GND,
      S  => GND );

  iIFD_6 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(6),
      Q2 => read_data_falling(6),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(6),
      R  => GND,
      S  => GND );

  iIFD_7 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(7),
      Q2 => read_data_falling(7),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(7),
      R  => GND,
      S  => GND );

end RTL;


-- ==============================================================
--  Module      : HE_DDR_A_IOB_D
--  Description : DDR Port A Data, Byte 3

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;


-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity HE_DDR_A_IOB_D is
  port (
    reset              : in  std_logic;
    clk180             : in  std_logic;
    wclk               : in  std_logic;
    dqs                : in  std_logic;
    write_en_val       : in  std_logic;
    read_en_val        : in  std_logic;
    write_data_rising  : in  std_logic_vector(7 downto 0);
    write_data_falling : in  std_logic_vector(7 downto 0);
    read_data_rising   : out std_logic_vector(7 downto 0);
    read_data_falling  : out std_logic_vector(7 downto 0);
    ddr_data_in        : in  std_logic_vector(7 downto 0);
    ddr_data_out       : out std_logic_vector(7 downto 0);
    ddr_data_en        : out std_logic_vector(7 downto 0)
  );
end HE_DDR_A_IOB_D;


architecture RTL of HE_DDR_A_IOB_D is

  component IDELAY
    generic(
      IOBDELAY_TYPE  : string := "VARIABLE";
      IOBDELAY_VALUE : integer := 0
    );
    port(
      O   : out std_ulogic;
      C   : in  std_ulogic;
      CE  : in  std_ulogic;
      I   : in  std_ulogic;
      INC : in  std_ulogic;
      RST : in  std_ulogic
    );
  end component;

  component IDDR
    generic(
      DDR_CLK_EDGE : string := "SAME_EDGE_PIPELINED";
      INIT_Q1      : bit    := '0';
      INIT_Q2      : bit    := '0';
      SRTYPE       : string := "SYNC"
    );
    port(
      Q1           : out std_ulogic;
      Q2           : out std_ulogic;
      C            : in  std_ulogic;
      CE           : in  std_ulogic;
      D            : in  std_ulogic;
      R            : in  std_ulogic;
      S            : in  std_ulogic
    );
  end component;

  component FDDRRSE
    port (
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  attribute IOB            : string;
  attribute IOBDELAY_TYPE  : string;
  attribute IOBDELAY_VALUE : integer;

  attribute DDR_CLK_EDGE   : string;
  attribute SRTYPE         : string;

  attribute IOB of iOEN_0  : label is "TRUE";
  attribute IOB of iOEN_1  : label is "TRUE";
  attribute IOB of iOEN_2  : label is "TRUE";
  attribute IOB of iOEN_3  : label is "TRUE";
  attribute IOB of iOEN_4  : label is "TRUE";
  attribute IOB of iOEN_5  : label is "TRUE";
  attribute IOB of iOEN_6  : label is "TRUE";
  attribute IOB of iOEN_7  : label is "TRUE";

  attribute IOBDELAY_TYPE  of iIDD_0 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_1 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_2 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_3 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_4 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_5 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_6 : label is "FIXED";
  attribute IOBDELAY_TYPE  of iIDD_7 : label is "FIXED";

  attribute IOBDELAY_VALUE of iIDD_0 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_1 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_2 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_3 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_4 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_5 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_6 : label is 12;
  attribute IOBDELAY_VALUE of iIDD_7 : label is 12;

  attribute DDR_CLK_EDGE of iIFD_0 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_1 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_2 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_3 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_4 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_5 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_6 : label is "SAME_EDGE_PIPELINED";
  attribute DDR_CLK_EDGE of iIFD_7 : label is "SAME_EDGE_PIPELINED";

  attribute SRTYPE of iIFD_0 : label is "SYNC";
  attribute SRTYPE of iIFD_1 : label is "SYNC";
  attribute SRTYPE of iIFD_2 : label is "SYNC";
  attribute SRTYPE of iIFD_3 : label is "SYNC";
  attribute SRTYPE of iIFD_4 : label is "SYNC";
  attribute SRTYPE of iIFD_5 : label is "SYNC";
  attribute SRTYPE of iIFD_6 : label is "SYNC";
  attribute SRTYPE of iIFD_7 : label is "SYNC";

  signal GND          : std_logic;
  signal VCC          : std_logic;

  signal wclkb        : std_logic;
  signal delayed_data : std_logic_vector(7 downto 0);

begin

  GND <= '0';
  VCC <= '1';

  wclkb <= not wclk;

  iOFD_0 : FDDRRSE port map (Q=>ddr_data_out(0), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(0), D1=>write_data_falling(0), R=>GND, S=>GND);
  iOFD_1 : FDDRRSE port map (Q=>ddr_data_out(1), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(1), D1=>write_data_falling(1), R=>GND, S=>GND);
  iOFD_2 : FDDRRSE port map (Q=>ddr_data_out(2), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(2), D1=>write_data_falling(2), R=>GND, S=>GND);
  iOFD_3 : FDDRRSE port map (Q=>ddr_data_out(3), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(3), D1=>write_data_falling(3), R=>GND, S=>GND);
  iOFD_4 : FDDRRSE port map (Q=>ddr_data_out(4), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(4), D1=>write_data_falling(4), R=>GND, S=>GND);
  iOFD_5 : FDDRRSE port map (Q=>ddr_data_out(5), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(5), D1=>write_data_falling(5), R=>GND, S=>GND);
  iOFD_6 : FDDRRSE port map (Q=>ddr_data_out(6), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(6), D1=>write_data_falling(6), R=>GND, S=>GND);
  iOFD_7 : FDDRRSE port map (Q=>ddr_data_out(7), C0=>wclk, C1=>wclkb, CE=>VCC, D0=>write_data_rising(7), D1=>write_data_falling(7), R=>GND, S=>GND);

  iOEN_0 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(0), CE=>VCC);
  iOEN_1 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(1), CE=>VCC);
  iOEN_2 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(2), CE=>VCC);
  iOEN_3 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(3), CE=>VCC);
  iOEN_4 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(4), CE=>VCC);
  iOEN_5 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(5), CE=>VCC);
  iOEN_6 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(6), CE=>VCC);
  iOEN_7 : FDCE port map (D=>write_en_val, CLR=>GND, C=>wclk, Q=>ddr_data_en(7), CE=>VCC);

  iIDD_0 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(0),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(0),
      INC => GND,
      RST => GND );

  iIDD_1 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(1),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(1),
      INC => GND,
      RST => GND );

  iIDD_2 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(2),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(2),
      INC => GND,
      RST => GND );

  iIDD_3 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(3),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(3),
      INC => GND,
      RST => GND );

  iIDD_4 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(4),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(4),
      INC => GND,
      RST => GND );

  iIDD_5 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(5),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(5),
      INC => GND,
      RST => GND );

  iIDD_6 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(6),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(6),
      INC => GND,
      RST => GND );

  iIDD_7 : IDELAY
    generic map (
      IOBDELAY_TYPE  => "FIXED",
      IOBDELAY_VALUE => 12 )
    port map (
      O   => delayed_data(7),
      C   => GND,
      CE  => GND,
      I   => ddr_data_in(7),
      INC => GND,
      RST => GND );

  iIFD_0 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(0),
      Q2 => read_data_falling(0),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(0),
      R  => GND,
      S  => GND );

  iIFD_1 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(1),
      Q2 => read_data_falling(1),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(1),
      R  => GND,
      S  => GND );

  iIFD_2 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(2),
      Q2 => read_data_falling(2),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(2),
      R  => GND,
      S  => GND );

  iIFD_3 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(3),
      Q2 => read_data_falling(3),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(3),
      R  => GND,
      S  => GND );

  iIFD_4 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(4),
      Q2 => read_data_falling(4),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(4),
      R  => GND,
      S  => GND );

  iIFD_5 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(5),
      Q2 => read_data_falling(5),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(5),
      R  => GND,
      S  => GND );

  iIFD_6 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(6),
      Q2 => read_data_falling(6),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(6),
      R  => GND,
      S  => GND );

  iIFD_7 : IDDR
    generic map (
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      INIT_Q1      => '0',
      INIT_Q2      => '0',
      SRTYPE       => "SYNC" )
    port map (
      Q1 => read_data_rising(7),
      Q2 => read_data_falling(7),
      C  => clk180,
      CE => read_en_val,
      D  => delayed_data(7),
      R  => GND,
      S  => GND );

end RTL;


-- ==============================================================
--  Module      : HE_DDR_DQS
--  Description : DDR Data Strobe

library IEEE;
  use IEEE.std_logic_1164.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity HE_DDR_DQS is
  port (
    DQS_enable  : in  std_logic;
    DQS_reset   : in  std_logic;
    clk         : in  std_logic;
    clk180      : in  std_logic;
    DDR_DQS_IN  : in  std_logic_vector(3 downto 0);
    DDR_DQS_OUT : out std_logic_vector(3 downto 0);
    DDR_DQS_EN  : out std_logic_vector(3 downto 0);
    DQS         : out std_logic_vector(3 downto 0)
  );
end HE_DDR_DQS;


architecture RTL of HE_DDR_DQS is

  component FD
    port(
      Q : out std_logic;
      D : in  std_logic;
      C : in  std_logic
    );
  end component;

  component FDDRRSE
    port(
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  attribute IOB : string;

  attribute IOB of iOEN_0 : label is "TRUE";
  attribute IOB of iOEN_1 : label is "TRUE";
  attribute IOB of iOEN_2 : label is "TRUE";
  attribute IOB of iOEN_3 : label is "TRUE";

  signal GND           : std_logic;
  signal VCC           : std_logic;

  signal DQS_reset_rg  : std_logic := '0';
  signal DQS_enable_rg : std_logic := '0';

begin

  VCC <= '1';
  GND <= '0';

  DQS(0) <= DDR_DQS_IN(0);
  DQS(1) <= DDR_DQS_IN(1);
  DQS(2) <= DDR_DQS_IN(2);
  DQS(3) <= DDR_DQS_IN(3);

  process(clk)
  begin
    if clk'event and clk='1' then
      DQS_reset_rg  <= DQS_reset;
      DQS_enable_rg <= DQS_enable;
    end if;
  end process;

  iOFD_0 : FDDRRSE
    port map (
      Q  => DDR_DQS_OUT(0),
      C0 => clk,
      C1 => clk180,
      CE => VCC,
      D0 => VCC,
      D1 => GND,
      R  => DQS_reset_rg,
      S  => GND );

  iOFD_1 : FDDRRSE
    port map (
      Q  => DDR_DQS_OUT(1),
      C0 => clk,
      C1 => clk180,
      CE => VCC,
      D0 => VCC,
      D1 => GND,
      R  => DQS_reset_rg,
      S  => GND );

  iOFD_2 : FDDRRSE
    port map (
      Q  => DDR_DQS_OUT(2),
      C0 => clk,
      C1 => clk180,
      CE => VCC,
      D0 => VCC,
      D1 => GND,
      R  => DQS_reset_rg,
      S  => GND );

  iOFD_3 : FDDRRSE
    port map (
      Q  => DDR_DQS_OUT(3),
      C0 => clk,
      C1 => clk180,
      CE => VCC,
      D0 => VCC,
      D1 => GND,
      R  => DQS_reset_rg,
      S  => GND );

  iOEN_0 : FD port map (D=>DQS_enable_rg, Q=>DDR_DQS_EN(0), C=>clk);
  iOEN_1 : FD port map (D=>DQS_enable_rg, Q=>DDR_DQS_EN(1), C=>clk);
  iOEN_2 : FD port map (D=>DQS_enable_rg, Q=>DDR_DQS_EN(2), C=>clk);
  iOEN_3 : FD port map (D=>DQS_enable_rg, Q=>DDR_DQS_EN(3), C=>clk);

end RTL;


-- ==============================================================
--  Module      : HE_DDR_DM_IOB
--  Description : DDR Data Mask

library IEEE;
  use IEEE.std_logic_1164.all;

-- pragma translate_off
library UNISIM;
  use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity HE_DDR_DM_IOB is
  port (
    write_data_mask_rising  : in  std_logic;
    write_data_mask_falling : in  std_logic;
    wclk                    : in  std_logic;
    reset                   : in  std_logic;
    write_en_val            : in  std_logic;
    ddr_dm_out              : out std_logic;
    ddr_dm_en               : out std_logic
  );
end HE_DDR_DM_IOB;


architecture RTL of HE_DDR_DM_IOB is

  component FDDRRSE
    port (
      Q  : out std_logic;
      C0 : in  std_logic;
      C1 : in  std_logic;
      CE : in  std_logic;
      D0 : in  std_logic;
      D1 : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic
    );
  end component;

  component FDCE
    port (
      D   : in  std_logic;
      CLR : in  std_logic;
      C   : in  std_logic;
      Q   : out std_logic;
      CE  : in  std_logic
    );
  end component;

  attribute IOB : string;

  attribute IOB of DQ_T : label is "TRUE";

  signal GND   : std_logic;
  signal VCC   : std_logic;

  signal wclkb : std_logic;

begin

  GND <= '0';
  VCC <= '1';

  wclkb <= not wclk;

  DDR_OUT : FDDRRSE
    port map (
      Q  => ddr_dm_out,
      C0 => wclk,
      C1 => wclkb,
      CE => VCC,
      D0 => write_data_mask_rising,
      D1 => write_data_mask_falling,
      R  => GND,
      S  => GND );

  DQ_T : FDCE
    port map (
      D   => write_en_val,
      CLR => GND,
      C   => wclk,
      Q   => ddr_dm_en,
      CE  => VCC );

end RTL;
