-- ==============================================================
-- FILE : TOP.VHD - may be modified by the ADVANCED USER
-- ==============================================================
--
-- This file is the top level of your project when using
-- Camera Link with the HERON-FPGA14 module.
--
-- This file could be modified by ADVANCED users.
--
-- ==============================================================
--
--  Module      : TOP
--  Date        : 06/04/2006
--  Author      : P. Warnes - HUNT ENGINEERING
--  Description : TOP level
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     P. Warnes      06-04-06    First Written for FPGA14
--  1.1     R. Williams    16-10-07    Added address enable to
--                                     user message interface to
--                                     improve response to bursts.
--
-- ==============================================================


library IEEE;
  use IEEE.std_logic_1164.all;
  use work.CONFIG.all;

-- synopsys translate_off
library UNISIM;
  use UNISIM.vcomponents.all;
-- synopsys translate_on

entity TOP is
  port (
    -- PADS - HE_WCLK
    doclk           : in  std_logic;                       -- FIFO_OUT clock (use with DLL)
    f0              : out std_logic;                       -- FIFO_OUT clock loop driver
    -- PADS - HE_WR_6F
    dof_ff          : in  std_logic_vector(5 downto 0);    -- FIFO_OUT full flag
    dof_af          : in  std_logic_vector(5 downto 0);    -- FIFO_OUT almost full flag
    dof_wen         : out std_logic_vector(5 downto 0);    -- FIFO_OUT write enable
    do              : out std_logic_vector(31 downto 0);   -- FIFO_OUT data
    -- PADS - HE_RCLK
    diclk           : in  std_logic;                       -- FIFO_IN clock (use with DLL)
    f1              : out std_logic;                       -- FIFO_IN clock loop driver
    -- PADS - HE_RD_6F
    dif_ef          : in  std_logic_vector(5 downto 0);    -- FIFO_IN empty flag
    dif_ae          : in  std_logic_vector(5 downto 0);    -- FIFO_IN almost empty flag
    dif_ren         : out std_logic_vector(5 downto 0);    -- FIFO_IN read enable
    dif_oen         : out std_logic_vector(5 downto 0);    -- FIFO_IN output enable
    di              : in  std_logic_vector(31 downto 0);   -- FIFO_IN data
    -- PADS - HE_DDR
    sdram_clkin     : in  std_logic;                       -- DDR SDRAM A Clock input
    sdram_a_clk_p   : out std_logic;                       -- DDR SDRAM A Clock Source
    sdram_a_clk_n   : out std_logic;                       -- DDR SDRAM A Clock Source complement
    sdram_a_a       : out std_logic_vector(13 downto 0);   -- DDR SDRAM A Address
    sdram_a_ba      : out std_logic_vector(1 downto 0);    -- DDR SDRAM A Bank Address
    sdram_a_dq      : inout std_logic_vector(31 downto 0):= (OTHERS => 'Z'); -- DDR A SDRAM Data
    sdram_a_dqs     : inout std_logic_vector(3 downto 0):= (OTHERS => 'Z');  -- DDR A SDRAM Data Strobes
    sdram_a_dm      : out std_logic_vector(3 downto 0);    -- DDR SDRAM A Data mask
    sdram_a_ras     : out std_logic;                       -- DDR SDRAM A Row address strobe
    sdram_a_cas     : out std_logic;                       -- DDR SDRAM A Col address strobe
    sdram_a_we      : out std_logic;                       -- DDR SDRAM A Write Enable   
    -- PADS - HSB
    adstrb          : in  std_logic;
    ad              : in  std_logic;
    rdwr            : in  std_logic;
    done            : out std_logic;
    ad_bus          : inout std_logic_vector(3 downto 0);
    mff             : in  std_logic;
    mack            : in  std_logic;
    mclk            : out std_logic;
    mdat            : out std_logic;
    -- PADS - Connector Digital I/O
    dio_a           : inout std_logic_vector(29 downto 0); -- Connector A IO
    dio_b           : inout std_logic_vector(29 downto 0); -- Connector B IO
    dio_c           : inout std_logic_vector(29 downto 0); -- Connector C IO
    dio_d           : inout std_logic_vector(29 downto 0); -- Connector D IO
    dio_e           : inout std_logic_vector(29 downto 0); -- Connector E IO
    dio_f           : inout std_logic_vector(29 downto 0); -- Connector F IO
    -- CONTROL signals
    config          : in  std_logic;                       -- config from carrier card
    reset_pin       : in  std_logic;                       -- reset from carrier card
    udpres          : out std_logic;                       -- reset the carrier (high if NOT used)
    -- OSC/CLOCKS
    osc0_pin        : in  std_logic;                       -- user oscillator from socketed Xtal Osc
    osc3_pin        : in  std_logic;                       -- user oscillator from surface mount Xtal Osc
    -- MISC I/O
    led             : out std_logic_vector(4 downto 0);    -- LEDs
    cid             : in  std_logic_vector(3 downto 0);    -- Carrier ID
    mid             : in  std_logic_vector(3 downto 0);    -- Module ID
    umi             : inout std_logic_vector(3 downto 0);  -- Uncommitted UMI interconnects
    module_has_proc : out std_logic                        -- Carrier signal
  );
end TOP;


architecture RTL of TOP is

  component IBUF
    port(I : in  std_logic;
         O : out std_logic);
  end component;

  component IBUFDS
    port(
      I  : in  std_logic;
      IB : in  std_logic;
      O  : out std_logic );
  end component;

  component OBUFDS
    port(
      I  : in  std_logic;
      O  : out std_logic;
      OB : out std_logic );
  end component;

  component IBUFGDS
    port(
      I  : in  std_logic;
      IB : in  std_logic;
      O  : out std_logic );
  end component;

  component IBUFG
    port(I : in  std_logic;
         O : out std_logic);
  end component;

  component IOBUF
    port(T  : in  std_logic;
         I  : in  std_logic;
         O  : out std_logic;
         IO : inout std_logic);
  end component;

  component OBUF
    port(I : in  std_logic;
         O : out std_logic);
  end component;

  component FDCP
     port (
       Q   : out std_logic;
       C   : in  std_logic;
       CLR : in  std_logic;
       D   : in  std_logic;
       PRE : in  std_logic);
  end component;

  component OBUFT
    port (I : in std_logic;
          T : in std_logic;
          O : out std_logic);
  end component;

  component PULLUP
   port(
      O : inout std_logic
      );
  end component;

  component HE_RWCLK
     port (
      -- PADS
      DCLK : in  std_logic;
      FCLK : out std_logic;
      -- I/O module
      RST  : in  std_logic;
      CLK  : in  std_logic;
      GCLK : out std_logic
    );
  end component;

  component HE_RD_6F
    port (
      -- PADS
      DIF_EF          : in  std_logic_vector(5 downto 0);
      DIF_AE          : in  std_logic_vector(5 downto 0);
      DIF_REN         : out std_logic_vector(5 downto 0);
      DIF_OEN         : out std_logic_vector(5 downto 0);
      DI              : in  std_logic_vector(31 downto 0);
      -- I/O module
      RST             : in  std_logic;
      CLK             : in  std_logic;
      INFIFO_READ_REQ : in  std_logic_vector(5 downto 0);
      INFIFO_DVALID   : out std_logic_vector(5 downto 0);
      INFIFO_SINGLE   : out std_logic_vector(5 downto 0);
      INFIFO_BURST    : out std_logic_vector(5 downto 0);
      INFIFO0_D       : out std_logic_vector(31 downto 0);
      INFIFO1_D       : out std_logic_vector(31 downto 0);
      INFIFO2_D       : out std_logic_vector(31 downto 0);
      INFIFO3_D       : out std_logic_vector(31 downto 0);
      INFIFO4_D       : out std_logic_vector(31 downto 0);
      INFIFO5_D       : out std_logic_vector(31 downto 0)
    );
  end component;

  component HE_WR_6F
    port (
      -- PADS
      DOF_FF        : in  std_logic_vector(5 downto 0);
      DOF_AF        : in  std_logic_vector(5 downto 0);
      DOF_WEN       : out std_logic_vector(5 downto 0);
      DO            : out std_logic_vector(31 downto 0);
      -- I/O module
      RST           : in  std_logic;
      CLK           : in  std_logic;
      OUTFIFO_WRITE : in  std_logic_vector(5 downto 0);
      OUTFIFO_D     : in  std_logic_vector(31 downto 0);
      OUTFIFO_READY : out std_logic_vector(5 downto 0)
    );
  end component;

  component HE_DDR
    port (
      -- PADS
      ddr_a_clk         : out std_logic;
      ddr_a_clkb        : out std_logic;
      ddr_a_address     : out std_logic_vector(13 downto 0);
      ddr_a_BA          : out std_logic_vector(1 downto 0);
      ddr_a_dq_in       : in  std_logic_vector(31 downto 0);
      ddr_a_dq_out      : out std_logic_vector(31 downto 0);
      ddr_a_dq_en       : out std_logic_vector(31 downto 0);
      ddr_a_dqs_in      : in  std_logic_vector(3 downto 0);
      ddr_a_dqs_out     : out std_logic_vector(3 downto 0);
      ddr_a_dqs_en      : out std_logic_vector(3 downto 0);
      ddr_a_dm_out      : out std_logic_vector(3 downto 0);
      ddr_a_dm_en       : out std_logic_vector(3 downto 0);
      ddr_a_rasb        : out std_logic;
      ddr_a_casb        : out std_logic;
      ddr_a_web         : out std_logic;
      -- Module I/Os
      user_input_clk    : in  std_logic;
      user_rst          : in  std_logic;
      -- DDR User Clock A
      DDR_A_USER_CLK    : in  std_logic;
      -- DDR User Reset A
      DDR_A_USER_RST    : in  std_logic;
      -- DDR Data Count
      DDR_A_DATA_COUNT  : out std_logic_vector(31 downto 0);
      -- DDR Write Port A
      DDR_A_WR_DATA     : in  std_logic_vector(71 downto 0);
      DDR_A_WR_ADDR     : in  std_logic_vector(24 downto 0);
      DDR_A_WR_ADDR_WEN : in  std_logic;
      DDR_A_WR_ADDR_FF  : out std_logic;
      DDR_A_WR_ADDR_AF  : out std_logic;
      DDR_A_WR_RISE_WEN : in  std_logic;
      DDR_A_WR_RISE_FF  : out std_logic;
      DDR_A_WR_RISE_AF  : out std_logic;
      DDR_A_WR_FALL_WEN : in  std_logic;
      DDR_A_WR_FALL_FF  : out std_logic;
      DDR_A_WR_FALL_AF  : out std_logic;
      DDR_A_WR_DM_WEN   : in  std_logic;
      DDR_A_WR_DM_FF    : out std_logic;
      DDR_A_WR_DM_AF    : out std_logic;
      -- DDR Read Port A
      DDR_A_RD_DATA     : out std_logic_vector(63 downto 0);
      DDR_A_RD_ADDR     : in  std_logic_vector(24 downto 0);
      DDR_A_RD_ADDR_WEN : in  std_logic;
      DDR_A_RD_ADDR_FF  : out std_logic;
      DDR_A_RD_ADDR_AF  : out std_logic;
      DDR_A_RD_RISE_REN : in  std_logic;
      DDR_A_RD_RISE_EF  : out std_logic;
      DDR_A_RD_RISE_AE  : out std_logic;
      DDR_A_RD_FALL_REN : in  std_logic;
      DDR_A_RD_FALL_EF  : out std_logic;
      DDR_A_RD_FALL_AE  : out std_logic
    );
  end component;

  component HE_USER
    port (
      -- PADS
      UADSTRB   : in  std_logic;
      UAD       : in  std_logic;
      URDWR     : in  std_logic;
      UAD_IN    : in  std_logic_vector(3 downto 0);
      UAD_EN    : out std_logic;
      UDONE     : out std_logic;
      UAD_OUT   : out std_logic_vector(3 downto 0);
      -- I/O module
      RST       : in  std_logic;
      CLK       : in  std_logic;
      MSG_READY : in  std_logic;
      MSG_DOUT  : in  std_logic_vector(7 downto 0);
      MSG_AEN   : out std_logic;
      MSG_WEN   : out std_logic;
      MSG_REN   : out std_logic;
      MSG_ADDR  : out std_logic_vector(7 downto 0);
      MSG_DIN   : out std_logic_vector(7 downto 0)
    );
  end component;

  component HE_MSG_MSTR
    port (
      -- PADS
      SFF           : in  std_logic;
      SACK          : in  std_logic;
      SCLK          : out std_logic;
      SDAT          : out std_logic;
      -- I/O module
      RST           : in  std_logic;
      CLK           : in  std_logic;
      CID           : in  std_logic_vector(3 downto 0);
      MID           : in  std_logic_vector(2 downto 0);
      MSG_SEND_MSG  : in  std_logic;
      MSG_SEND_ID   : in  std_logic;
      MSG_LAST_BYTE : in  std_logic;
      MSG_DOUT      : in  std_logic_vector(7 downto 0);
      MSG_DONE      : out std_logic;
      MSG_COUNT     : out std_logic;
      MSG_CLEAR     : out std_logic
    );
  end component;

  component USER_AP
    port (
      RESET             : in  std_logic;
      CONFIG            : in  std_logic;
  -- CLOCK SIGNALS
      OSC0              : in  std_logic;
      OSC3              : in  std_logic;
  -- GENERAL IO
      UDPRES            : out std_logic;
      LED               : out std_logic_vector(4 downto 0);
      MOD_HAS_PROC      : out  std_logic;
      CID               : in  std_logic_vector(3 downto 0);
      MID               : in  std_logic_vector(3 downto 0);
  -- UMIs
      UMI_IN            : in  std_logic_vector(3 downto 0);
      UMI_OUT           : out std_logic_vector(3 downto 0);
      UMI_EN            : out std_logic_vector(3 downto 0);
  -- READ FIFO CLK
      FCLK_RD           : in  std_logic;
      SRC_FCLK_RD       : out std_logic;
  -- WRITE FIFO CLK
      FCLK_WR           : in  std_logic;
      SRC_FCLK_WR       : out std_logic;
  -- GLOBAL FIFO CLK
      FCLK_G            : in  std_logic;
      SRC_FCLK_G        : out std_logic;
  -- FIFO IN / HE_RD_6F interface
      INFIFO_READ_REQ   : out std_logic_vector(5 downto 0);
      INFIFO_DVALID     : in  std_logic_vector(5 downto 0);
      INFIFO_SINGLE     : in  std_logic_vector(5 downto 0);
      INFIFO_BURST      : in  std_logic_vector(5 downto 0);
      INFIFO0_D         : in  std_logic_vector(31 downto 0);
      INFIFO1_D         : in  std_logic_vector(31 downto 0);
      INFIFO2_D         : in  std_logic_vector(31 downto 0);
      INFIFO3_D         : in  std_logic_vector(31 downto 0);
      INFIFO4_D         : in  std_logic_vector(31 downto 0);
      INFIFO5_D         : in  std_logic_vector(31 downto 0);
  -- FIFO OUT / HE_WR_6F interface
      OUTFIFO_READY     : in  std_logic_vector(5 downto 0);
      OUTFIFO_WRITE     : out std_logic_vector(5 downto 0);
      OUTFIFO_D         : out std_logic_vector(31 downto 0);
  -- SERIAL BUS / HE_USER interface
      MSG_CLK           : out std_logic;
      MSG_DIN           : in  std_logic_vector(7 downto 0);
      MSG_ADDR          : in  std_logic_vector(7 downto 0);
      MSG_AEN           : in  std_logic;
      MSG_WEN           : in  std_logic;
      MSG_REN           : in  std_logic;
      MSG_DONE          : in  std_logic;
      MSG_COUNT         : in  std_logic;
      MSG_CLEAR         : in  std_logic;
      MSG_READY         : out std_logic;
      MSG_SEND_MSG      : out std_logic;
      MSG_CE            : out std_logic;
      MSG_DOUT          : out std_logic_vector(7 downto 0);
      MSG_SEND_ID       : out std_logic;
      MSG_LAST_BYTE     : out std_logic;
      CAM_CLK           : in  std_logic;                      -- Camera Link Clock
      CAM_DATA          : in  std_logic_vector(3  downto 0);  -- Camera Link Data
      CAM_CTRL          : out std_logic_vector(3  downto 0);  -- Camera Link Control
      CAM_SER_TC        : out std_logic;                      -- Camera Link Serial Out
      CAM_SER_TFG       : in  std_logic;                      -- Camera Link Serial In
  -- CONNECTOR DIGITAL IO
      CONN_A_IN         : in  std_logic_vector(29 downto 22);
      CONN_A_OUT        : out std_logic_vector(29 downto 22);
      CONN_A_EN         : out std_logic_vector(29 downto 22);
      CONN_B_IN         : in  std_logic_vector(29 downto 0);
      CONN_B_OUT        : out std_logic_vector(29 downto 0);
      CONN_B_EN         : out std_logic_vector(29 downto 0);
      CONN_C_IN         : in  std_logic_vector(29 downto 0);
      CONN_C_OUT        : out std_logic_vector(29 downto 0);
      CONN_C_EN         : out std_logic_vector(29 downto 0);
      CONN_D_IN         : in  std_logic_vector(29 downto 0);
      CONN_D_OUT        : out std_logic_vector(29 downto 0);
      CONN_D_EN         : out std_logic_vector(29 downto 0);
      CONN_E_IN         : in  std_logic_vector(29 downto 0);
      CONN_E_OUT        : out std_logic_vector(29 downto 0);
      CONN_E_EN         : out std_logic_vector(29 downto 0);
      CONN_F_IN         : in  std_logic_vector(29 downto 0);
      CONN_F_OUT        : out std_logic_vector(29 downto 0);
      CONN_F_EN         : out std_logic_vector(29 downto 0);
  -- DDR User Clock A
      DDR_A_USER_CLK    : out std_logic;
  -- DDR User Reset A
      DDR_A_USER_RST    : out std_logic;
  -- DDR Data Count
      DDR_A_DATA_COUNT  : in  std_logic_vector(31 downto 0);
  -- DDR Write Port A
      DDR_A_WR_DATA     : out std_logic_vector(71 downto 0);
      DDR_A_WR_ADDR     : out std_logic_vector(24 downto 0);
      DDR_A_WR_ADDR_WEN : out std_logic;
      DDR_A_WR_ADDR_FF  : in  std_logic;
      DDR_A_WR_ADDR_AF  : in  std_logic;
      DDR_A_WR_RISE_WEN : out std_logic;
      DDR_A_WR_RISE_FF  : in  std_logic;
      DDR_A_WR_RISE_AF  : in  std_logic;
      DDR_A_WR_FALL_WEN : out std_logic;
      DDR_A_WR_FALL_FF  : in  std_logic;
      DDR_A_WR_FALL_AF  : in  std_logic;
      DDR_A_WR_DM_WEN   : out std_logic;
      DDR_A_WR_DM_FF    : in  std_logic;
      DDR_A_WR_DM_AF    : in  std_logic;
  -- DDR Read Port A
      DDR_A_RD_DATA     : in  std_logic_vector(63 downto 0);
      DDR_A_RD_ADDR     : out std_logic_vector(24 downto 0);
      DDR_A_RD_ADDR_WEN : out std_logic;
      DDR_A_RD_ADDR_FF  : in  std_logic;
      DDR_A_RD_ADDR_AF  : in  std_logic;
      DDR_A_RD_RISE_REN : out std_logic;
      DDR_A_RD_RISE_EF  : in  std_logic;
      DDR_A_RD_RISE_AE  : in  std_logic;
      DDR_A_RD_FALL_REN : out std_logic;
      DDR_A_RD_FALL_EF  : in  std_logic;
      DDR_A_RD_FALL_AE  : in  std_logic
    );
  end component;

  attribute IOSTANDARD : string;
  attribute DRIVE      : string;
  attribute FAST       : string;
  attribute IOB        : string;

  attribute DIFF_TERM  : string;

  -- Write Clock and Read Clock Buffer Definitions
  attribute FAST of oF0  : label is "TRUE";
  attribute FAST of oF1  : label is "TRUE";

  attribute DRIVE of oF0 : label is "24";
  attribute DRIVE of oF1 : label is "24";

  attribute IOSTANDARD of oF0    : label is "LVTTL";
  attribute IOSTANDARD of oF1    : label is "LVTTL";

  attribute IOSTANDARD of iDICLK : label is "LVTTL";
  attribute IOSTANDARD of iDOCLK : label is "LVTTL";

  -- Write FIFO Interface Buffer Definitions
  attribute IOSTANDARD of oDO0  : label is "LVTTL";
  attribute IOSTANDARD of oDO1  : label is "LVTTL";
  attribute IOSTANDARD of oDO2  : label is "LVTTL";
  attribute IOSTANDARD of oDO3  : label is "LVTTL";
  attribute IOSTANDARD of oDO4  : label is "LVTTL";
  attribute IOSTANDARD of oDO5  : label is "LVTTL";
  attribute IOSTANDARD of oDO6  : label is "LVTTL";
  attribute IOSTANDARD of oDO7  : label is "LVTTL";
  attribute IOSTANDARD of oDO8  : label is "LVTTL";
  attribute IOSTANDARD of oDO9  : label is "LVTTL";
  attribute IOSTANDARD of oDO10 : label is "LVTTL";
  attribute IOSTANDARD of oDO11 : label is "LVTTL";
  attribute IOSTANDARD of oDO12 : label is "LVTTL";
  attribute IOSTANDARD of oDO13 : label is "LVTTL";
  attribute IOSTANDARD of oDO14 : label is "LVTTL";
  attribute IOSTANDARD of oDO15 : label is "LVTTL";
  attribute IOSTANDARD of oDO16 : label is "LVTTL";
  attribute IOSTANDARD of oDO17 : label is "LVTTL";
  attribute IOSTANDARD of oDO18 : label is "LVTTL";
  attribute IOSTANDARD of oDO19 : label is "LVTTL";
  attribute IOSTANDARD of oDO20 : label is "LVTTL";
  attribute IOSTANDARD of oDO21 : label is "LVTTL";
  attribute IOSTANDARD of oDO22 : label is "LVTTL";
  attribute IOSTANDARD of oDO23 : label is "LVTTL";
  attribute IOSTANDARD of oDO24 : label is "LVTTL";
  attribute IOSTANDARD of oDO25 : label is "LVTTL";
  attribute IOSTANDARD of oDO26 : label is "LVTTL";
  attribute IOSTANDARD of oDO27 : label is "LVTTL";
  attribute IOSTANDARD of oDO28 : label is "LVTTL";
  attribute IOSTANDARD of oDO29 : label is "LVTTL";
  attribute IOSTANDARD of oDO30 : label is "LVTTL";
  attribute IOSTANDARD of oDO31 : label is "LVTTL";

  attribute IOSTANDARD of iFF0 : label is "LVTTL";
  attribute IOSTANDARD of iFF1 : label is "LVTTL";
  attribute IOSTANDARD of iFF2 : label is "LVTTL";
  attribute IOSTANDARD of iFF3 : label is "LVTTL";
  attribute IOSTANDARD of iFF4 : label is "LVTTL";
  attribute IOSTANDARD of iFF5 : label is "LVTTL";

  attribute IOSTANDARD of iAF0 : label is "LVTTL";
  attribute IOSTANDARD of iAF1 : label is "LVTTL";
  attribute IOSTANDARD of iAF2 : label is "LVTTL";
  attribute IOSTANDARD of iAF3 : label is "LVTTL";
  attribute IOSTANDARD of iAF4 : label is "LVTTL";
  attribute IOSTANDARD of iAF5 : label is "LVTTL";

  attribute IOSTANDARD of oWEN0 : label is "LVTTL";
  attribute IOSTANDARD of oWEN1 : label is "LVTTL";
  attribute IOSTANDARD of oWEN2 : label is "LVTTL";
  attribute IOSTANDARD of oWEN3 : label is "LVTTL";
  attribute IOSTANDARD of oWEN4 : label is "LVTTL";
  attribute IOSTANDARD of oWEN5 : label is "LVTTL";

  attribute FAST of oWEN0 : label is "TRUE";
  attribute FAST of oWEN1 : label is "TRUE";
  attribute FAST of oWEN2 : label is "TRUE";
  attribute FAST of oWEN3 : label is "TRUE";
  attribute FAST of oWEN4 : label is "TRUE";
  attribute FAST of oWEN5 : label is "TRUE";

  attribute DRIVE of oWEN0 : label is "8";
  attribute DRIVE of oWEN1 : label is "8";
  attribute DRIVE of oWEN2 : label is "8";
  attribute DRIVE of oWEN3 : label is "8";
  attribute DRIVE of oWEN4 : label is "8";
  attribute DRIVE of oWEN5 : label is "8";

  -- Read FIFO Interface Buffer Definitions
  attribute IOSTANDARD of iDI0  : label is "LVTTL";
  attribute IOSTANDARD of iDI1  : label is "LVTTL";
  attribute IOSTANDARD of iDI2  : label is "LVTTL";
  attribute IOSTANDARD of iDI3  : label is "LVTTL";
  attribute IOSTANDARD of iDI4  : label is "LVTTL";
  attribute IOSTANDARD of iDI5  : label is "LVTTL";
  attribute IOSTANDARD of iDI6  : label is "LVTTL";
  attribute IOSTANDARD of iDI7  : label is "LVTTL";
  attribute IOSTANDARD of iDI8  : label is "LVTTL";
  attribute IOSTANDARD of iDI9  : label is "LVTTL";
  attribute IOSTANDARD of iDI10 : label is "LVTTL";
  attribute IOSTANDARD of iDI11 : label is "LVTTL";
  attribute IOSTANDARD of iDI12 : label is "LVTTL";
  attribute IOSTANDARD of iDI13 : label is "LVTTL";
  attribute IOSTANDARD of iDI14 : label is "LVTTL";
  attribute IOSTANDARD of iDI15 : label is "LVTTL";
  attribute IOSTANDARD of iDI16 : label is "LVTTL";
  attribute IOSTANDARD of iDI17 : label is "LVTTL";
  attribute IOSTANDARD of iDI18 : label is "LVTTL";
  attribute IOSTANDARD of iDI19 : label is "LVTTL";
  attribute IOSTANDARD of iDI20 : label is "LVTTL";
  attribute IOSTANDARD of iDI21 : label is "LVTTL";
  attribute IOSTANDARD of iDI22 : label is "LVTTL";
  attribute IOSTANDARD of iDI23 : label is "LVTTL";
  attribute IOSTANDARD of iDI24 : label is "LVTTL";
  attribute IOSTANDARD of iDI25 : label is "LVTTL";
  attribute IOSTANDARD of iDI26 : label is "LVTTL";
  attribute IOSTANDARD of iDI27 : label is "LVTTL";
  attribute IOSTANDARD of iDI28 : label is "LVTTL";
  attribute IOSTANDARD of iDI29 : label is "LVTTL";
  attribute IOSTANDARD of iDI30 : label is "LVTTL";
  attribute IOSTANDARD of iDI31 : label is "LVTTL";

  attribute IOSTANDARD of iEF0 : label is "LVTTL";
  attribute IOSTANDARD of iEF1 : label is "LVTTL";
  attribute IOSTANDARD of iEF2 : label is "LVTTL";
  attribute IOSTANDARD of iEF3 : label is "LVTTL";
  attribute IOSTANDARD of iEF4 : label is "LVTTL";
  attribute IOSTANDARD of iEF5 : label is "LVTTL";

  attribute IOSTANDARD of iAE0 : label is "LVTTL";
  attribute IOSTANDARD of iAE1 : label is "LVTTL";
  attribute IOSTANDARD of iAE2 : label is "LVTTL";
  attribute IOSTANDARD of iAE3 : label is "LVTTL";
  attribute IOSTANDARD of iAE4 : label is "LVTTL";
  attribute IOSTANDARD of iAE5 : label is "LVTTL";

  attribute IOSTANDARD of oREN0 : label is "LVTTL";
  attribute IOSTANDARD of oREN1 : label is "LVTTL";
  attribute IOSTANDARD of oREN2 : label is "LVTTL";
  attribute IOSTANDARD of oREN3 : label is "LVTTL";
  attribute IOSTANDARD of oREN4 : label is "LVTTL";
  attribute IOSTANDARD of oREN5 : label is "LVTTL";

  attribute IOSTANDARD of oOEN0 : label is "LVTTL";
  attribute IOSTANDARD of oOEN1 : label is "LVTTL";
  attribute IOSTANDARD of oOEN2 : label is "LVTTL";
  attribute IOSTANDARD of oOEN3 : label is "LVTTL";
  attribute IOSTANDARD of oOEN4 : label is "LVTTL";
  attribute IOSTANDARD of oOEN5 : label is "LVTTL";

  attribute FAST of oREN0 : label is "TRUE";
  attribute FAST of oREN1 : label is "TRUE";
  attribute FAST of oREN2 : label is "TRUE";
  attribute FAST of oREN3 : label is "TRUE";
  attribute FAST of oREN4 : label is "TRUE";
  attribute FAST of oREN5 : label is "TRUE";

  attribute FAST of oOEN0 : label is "TRUE";
  attribute FAST of oOEN1 : label is "TRUE";
  attribute FAST of oOEN2 : label is "TRUE";
  attribute FAST of oOEN3 : label is "TRUE";
  attribute FAST of oOEN4 : label is "TRUE";
  attribute FAST of oOEN5 : label is "TRUE";

  attribute DRIVE of oREN0 : label is "8";
  attribute DRIVE of oREN1 : label is "8";
  attribute DRIVE of oREN2 : label is "8";
  attribute DRIVE of oREN3 : label is "8";
  attribute DRIVE of oREN4 : label is "8";
  attribute DRIVE of oREN5 : label is "8";

  attribute DRIVE of oOEN0 : label is "8";
  attribute DRIVE of oOEN1 : label is "8";
  attribute DRIVE of oOEN2 : label is "8";
  attribute DRIVE of oOEN3 : label is "8";
  attribute DRIVE of oOEN4 : label is "8";
  attribute DRIVE of oOEN5 : label is "8";

  -- DDR SDRAM Interface Buffer Definitions
  attribute IOSTANDARD of iSCLKI : label is "LVTTL";

  attribute IOSTANDARD of oSCLK_A0 : label is "SSTL2_I";
  attribute IOSTANDARD of oSCLK_A1 : label is "SSTL2_I";

  attribute IOSTANDARD of oSD_A_AD0  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD1  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD2  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD3  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD4  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD5  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD6  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD7  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD8  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD9  : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD10 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD11 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD12 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_AD13 : label is "SSTL2_I";

  attribute IOSTANDARD of oSD_A_BA0 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_BA1 : label is "SSTL2_I";

  attribute IOSTANDARD of iSD_A_D0  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D1  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D2  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D3  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D4  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D5  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D6  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D7  : label is "SSTL2_II";

  attribute IOSTANDARD of iSD_A_D8  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D9  : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D10 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D11 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D12 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D13 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D14 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D15 : label is "SSTL2_II";

  attribute IOSTANDARD of iSD_A_D16 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D17 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D18 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D19 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D20 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D21 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D22 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D23 : label is "SSTL2_II";

  attribute IOSTANDARD of iSD_A_D24 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D25 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D26 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D27 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D28 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D29 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D30 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_D31 : label is "SSTL2_II";

  attribute IOSTANDARD of iSD_A_DQS0 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_DQS1 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_DQS2 : label is "SSTL2_II";
  attribute IOSTANDARD of iSD_A_DQS3 : label is "SSTL2_II";

  attribute IOSTANDARD of oSD_A_DM0 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_DM1 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_DM2 : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_DM3 : label is "SSTL2_I";

  attribute IOSTANDARD of oSD_A_RAS : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_CAS : label is "SSTL2_I";
  attribute IOSTANDARD of oSD_A_WE  : label is "SSTL2_I";

  -- HSB/User Interface Buffer Definitions
  attribute IOSTANDARD of iADSTRB : label is "LVCMOS25";
  attribute IOSTANDARD of iAD     : label is "LVCMOS25";
  attribute IOSTANDARD of iRDWR   : label is "LVCMOS25";
  attribute IOSTANDARD of iDONE   : label is "LVCMOS25";

  attribute IOB        of iADSTRB : label is "TRUE";
  attribute IOB        of iAD     : label is "TRUE";
  attribute IOB        of iRDWR   : label is "TRUE";
  attribute IOB        of iDONE   : label is "TRUE";

  attribute IOSTANDARD of iAD0    : label is "LVCMOS25";
  attribute IOSTANDARD of iAD1    : label is "LVCMOS25";
  attribute IOSTANDARD of iAD2    : label is "LVCMOS25";
  attribute IOSTANDARD of iAD3    : label is "LVCMOS25";

  attribute IOSTANDARD of iMFF    : label is "LVCMOS25";
  attribute IOSTANDARD of iMACK   : label is "LVCMOS25";
  attribute IOSTANDARD of iMCLK   : label is "LVCMOS25";
  attribute IOSTANDARD of iMDAT   : label is "LVCMOS25";

  attribute DRIVE      of iMCLK   : label is "8";
  attribute DRIVE      of iMDAT   : label is "8";

  attribute FAST       of iMCLK   : label is "TRUE";
  attribute FAST       of iMDAT   : label is "TRUE";

  -- Digital I/O Buffer Definitions

  -- NOTE : Signals 0 to 21 on Connector A are used for Camera Link
  attribute IOSTANDARD of iDIOA22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOA29 : label is "LVTTL";

  attribute IOSTANDARD of iDIOB0  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB1  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB2  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB3  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB4  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB5  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB6  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB7  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB8  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB9  : label is "LVTTL";
  attribute IOSTANDARD of iDIOB10 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB11 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB12 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB13 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB14 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB15 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB16 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB17 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB18 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB19 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB20 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB21 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOB29 : label is "LVTTL";

  attribute IOSTANDARD of iDIOC0  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC1  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC2  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC3  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC4  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC5  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC6  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC7  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC8  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC9  : label is "LVTTL";
  attribute IOSTANDARD of iDIOC10 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC11 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC12 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC13 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC14 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC15 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC16 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC17 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC18 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC19 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC20 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC21 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOC29 : label is "LVTTL";

  attribute IOSTANDARD of iDIOD0  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD1  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD2  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD3  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD4  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD5  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD6  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD7  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD8  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD9  : label is "LVTTL";
  attribute IOSTANDARD of iDIOD10 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD11 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD12 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD13 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD14 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD15 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD16 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD17 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD18 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD19 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD20 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD21 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOD29 : label is "LVTTL";

  attribute IOSTANDARD of iDIOE0  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE1  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE2  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE3  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE4  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE5  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE6  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE7  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE8  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE9  : label is "LVTTL";
  attribute IOSTANDARD of iDIOE10 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE11 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE12 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE13 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE14 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE15 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE16 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE17 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE18 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE19 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE20 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE21 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOE29 : label is "LVTTL";

  attribute IOSTANDARD of iDIOF0  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF1  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF2  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF3  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF4  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF5  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF6  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF7  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF8  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF9  : label is "LVTTL";
  attribute IOSTANDARD of iDIOF10 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF11 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF12 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF13 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF14 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF15 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF16 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF17 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF18 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF19 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF20 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF21 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF22 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF23 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF24 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF25 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF26 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF27 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF28 : label is "LVTTL";
  attribute IOSTANDARD of iDIOF29 : label is "LVTTL";

  -- Control Signal Buffer Definitions
  attribute IOSTANDARD of iCFG : label is "LVTTL";
  attribute IOSTANDARD of iRES : label is "LVTTL";
  attribute IOSTANDARD of oUDP : label is "LVTTL";

  -- OSC/Clocks Buffer Definitions
  attribute IOSTANDARD of iOSC0 : label is "LVTTL";
  attribute IOSTANDARD of iOSC3 : label is "LVTTL";

  -- Misc. I/O Buffer Definitions
  attribute IOSTANDARD of oLED0 : label is "LVCMOS25";
  attribute IOSTANDARD of oLED1 : label is "LVCMOS25";
  attribute IOSTANDARD of oLED2 : label is "LVCMOS25";
  attribute IOSTANDARD of oLED3 : label is "LVTTL";
  attribute IOSTANDARD of oLED4 : label is "LVTTL";

  attribute IOSTANDARD of iCID0 : label is "LVTTL";
  attribute IOSTANDARD of iCID1 : label is "LVTTL";
  attribute IOSTANDARD of iCID2 : label is "LVTTL";
  attribute IOSTANDARD of iCID3 : label is "LVTTL";

  attribute IOSTANDARD of iMID0 : label is "LVTTL";
  attribute IOSTANDARD of iMID1 : label is "LVTTL";
  attribute IOSTANDARD of iMID2 : label is "LVTTL";
  attribute IOSTANDARD of iMID3 : label is "LVTTL";

  attribute IOSTANDARD of iUMI0 : label is "LVTTL";
  attribute IOSTANDARD of iUMI1 : label is "LVTTL";
  attribute IOSTANDARD of iUMI2 : label is "LVTTL";
  attribute IOSTANDARD of iUMI3 : label is "LVTTL";

  attribute IOSTANDARD of iAFS  : label is "LVTTL";

  -- Camera Link Buffer Definitions
  attribute IOSTANDARD of lvds_ibufg : label is "LVDS_25";

  attribute IOSTANDARD of lvds_ibuf0 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_ibuf1 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_ibuf2 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_ibuf3 : label is "LVDS_25";

  attribute IOSTANDARD of lvds_obuf0 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_obuf1 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_obuf2 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_obuf3 : label is "LVDS_25";

  attribute IOSTANDARD of lvds_obuf4 : label is "LVDS_25";
  attribute IOSTANDARD of lvds_ibuf4 : label is "LVDS_25";

  attribute DIFF_TERM  of lvds_ibufg : label is "TRUE";

  attribute DIFF_TERM  of lvds_ibuf0 : label is "TRUE";
  attribute DIFF_TERM  of lvds_ibuf1 : label is "TRUE";
  attribute DIFF_TERM  of lvds_ibuf2 : label is "TRUE";
  attribute DIFF_TERM  of lvds_ibuf3 : label is "TRUE";

  attribute DIFF_TERM  of lvds_ibuf4 : label is "TRUE";

  signal xLED              : std_logic_vector(4 downto 0);
  signal xCID              : std_logic_vector(3 downto 0);
  signal xMID              : std_logic_vector(3 downto 0);
  signal xRESET            : std_logic;
  signal xCONFIG           : std_logic;
  signal xUDPRES           : std_logic;
  signal xMOD_HAS_PROC     : std_logic;
  signal RESET             : std_logic;

  signal OSC0              : std_logic;
  signal OSC3              : std_logic;

  signal FCLK_RD           : std_logic;
  signal SRC_FCLK_RD       : std_logic;
  signal FCLK_WR           : std_logic;
  signal SRC_FCLK_WR       : std_logic;
  signal FCLK_G            : std_logic;
  signal xFCLK_G           : std_logic;
  signal SRC_FCLK_G        : std_logic;
  signal xDICLK            : std_logic;
  signal xF1               : std_logic;
  signal xDOCLK            : std_logic;
  signal xF0               : std_logic;

  signal xDIF_EF           : std_logic_vector(5 downto 0);
  signal xDIF_AE           : std_logic_vector(5 downto 0);
  signal xDIF_REN          : std_logic_vector(5 downto 0);
  signal xDIF_OEN          : std_logic_vector(5 downto 0);
  signal xDI               : std_logic_vector(31 downto 0);
  signal INFIFO_READ_REQ   : std_logic_vector(5 downto 0);
  signal INFIFO_DVALID     : std_logic_vector(5 downto 0);
  signal INFIFO_SINGLE     : std_logic_vector(5 downto 0);
  signal INFIFO_BURST      : std_logic_vector(5 downto 0);
  signal INFIFO0_D         : std_logic_vector(31 downto 0);
  signal INFIFO1_D         : std_logic_vector(31 downto 0);
  signal INFIFO2_D         : std_logic_vector(31 downto 0);
  signal INFIFO3_D         : std_logic_vector(31 downto 0);
  signal INFIFO4_D         : std_logic_vector(31 downto 0);
  signal INFIFO5_D         : std_logic_vector(31 downto 0);

  signal xDOF_FF           : std_logic_vector(5 downto 0);
  signal xDOF_AF           : std_logic_vector(5 downto 0);
  signal xDOF_WEN          : std_logic_vector(5 downto 0);
  signal xDO               : std_logic_vector(31 downto 0);
  signal OUTFIFO_READY     : std_logic_vector(5 downto 0);
  signal OUTFIFO_WRITE     : std_logic_vector(5 downto 0);
  signal OUTFIFO_D         : std_logic_vector(31 downto 0);

  signal UADSTRB           : std_logic;
  signal UAD               : std_logic;
  signal URDWR             : std_logic;
  signal UAD_EN            : std_logic;
  signal UAD_i             : std_logic_vector(3 downto 0);
  signal UAD_IN            : std_logic_vector(3 downto 0);
  signal UDONE             : std_logic;
  signal UAD_OUT           : std_logic_vector(3 downto 0);

  signal SFF               : std_logic;
  signal SACK              : std_logic;
  signal SCLK              : std_logic;
  signal SDAT              : std_logic;

  signal MSG_CLK           : std_logic;
  signal MSG_READY         : std_logic;
  signal MSG_SEND_MSG      : std_logic;
  signal MSG_CE            : std_logic;
  signal MSG_DOUT          : std_logic_vector(7 downto 0);
  signal MSG_SEND_ID       : std_logic;
  signal MSG_LAST_BYTE     : std_logic;
  signal MSG_DIN           : std_logic_vector(7 downto 0);
  signal MSG_ADDR          : std_logic_vector(7 downto 0);
  signal MSG_AEN           : std_logic;
  signal MSG_WEN           : std_logic;
  signal MSG_REN           : std_logic;
  signal MSG_DONE          : std_logic;
  signal MSG_COUNT         : std_logic;
  signal MSG_CLEAR         : std_logic;

  signal UMI_IN            : std_logic_vector(3 downto 0);
  signal UMI_OUT           : std_logic_vector(3 downto 0);
  signal UMI_EN            : std_logic_vector(3 downto 0);

  signal CAM_CLK           : std_logic;
  signal CAM_DATA          : std_logic_vector(3 downto 0);
  signal CAM_CTRL          : std_logic_vector(3 downto 0);
  signal CAM_SER_TC        : std_logic;
  signal CAM_SER_TFG       : std_logic;

  -- NOTE : Signals 0 to 21 on Connector A are used for Camera Link
  signal CONN_A_IN         : std_logic_vector(29 downto 22);
  signal CONN_A_OUT        : std_logic_vector(29 downto 22);
  signal CONN_A_EN         : std_logic_vector(29 downto 22);

  signal CONN_B_IN         : std_logic_vector(29 downto 0);
  signal CONN_B_OUT        : std_logic_vector(29 downto 0);
  signal CONN_B_EN         : std_logic_vector(29 downto 0);

  signal CONN_C_IN         : std_logic_vector(29 downto 0);
  signal CONN_C_OUT        : std_logic_vector(29 downto 0);
  signal CONN_C_EN         : std_logic_vector(29 downto 0);

  signal CONN_D_IN         : std_logic_vector(29 downto 0);
  signal CONN_D_OUT        : std_logic_vector(29 downto 0);
  signal CONN_D_EN         : std_logic_vector(29 downto 0);

  signal CONN_E_IN         : std_logic_vector(29 downto 0);
  signal CONN_E_OUT        : std_logic_vector(29 downto 0);
  signal CONN_E_EN         : std_logic_vector(29 downto 0);

  signal CONN_F_IN         : std_logic_vector(29 downto 0);
  signal CONN_F_OUT        : std_logic_vector(29 downto 0);
  signal CONN_F_EN         : std_logic_vector(29 downto 0);

  signal user_input_clk    : std_logic;

  signal ddr_a_clk         : std_logic;
  signal ddr_a_clkb        : std_logic;
  signal ddr_a_address     : std_logic_vector(13 downto 0);
  signal ddr_a_BA          : std_logic_vector(1 downto 0);
  signal ddr_a_dq_in       : std_logic_vector(31 downto 0);
  signal ddr_a_dq_out      : std_logic_vector(31 downto 0);
  signal ddr_a_dq_en       : std_logic_vector(31 downto 0);
  signal ddr_a_dqs_in      : std_logic_vector(3 downto 0);
  signal ddr_a_dqs_out     : std_logic_vector(3 downto 0);
  signal ddr_a_dqs_en      : std_logic_vector(3 downto 0);
  signal ddr_a_dm_out      : std_logic_vector(3 downto 0);
  signal ddr_a_dm_en       : std_logic_vector(3 downto 0);
  signal ddr_a_rasb        : std_logic;
  signal ddr_a_casb        : std_logic;
  signal ddr_a_web         : std_logic;
  signal ddr_a_dx          : std_logic;

  signal DDR_A_USER_CLK    : std_logic;

  signal DDR_A_USER_RST    : std_logic;

  signal DDR_A_DATA_COUNT  : std_logic_vector(31 downto 0);

  signal DDR_A_WR_DATA     : std_logic_vector(71 downto 0);
  signal DDR_A_WR_ADDR     : std_logic_vector(24 downto 0);
  signal DDR_A_WR_ADDR_WEN : std_logic;
  signal DDR_A_WR_ADDR_FF  : std_logic;
  signal DDR_A_WR_ADDR_AF  : std_logic;
  signal DDR_A_WR_RISE_WEN : std_logic;
  signal DDR_A_WR_RISE_FF  : std_logic;
  signal DDR_A_WR_RISE_AF  : std_logic;
  signal DDR_A_WR_FALL_WEN : std_logic;
  signal DDR_A_WR_FALL_FF  : std_logic;
  signal DDR_A_WR_FALL_AF  : std_logic;
  signal DDR_A_WR_DM_WEN   : std_logic;
  signal DDR_A_WR_DM_FF    : std_logic;
  signal DDR_A_WR_DM_AF    : std_logic;

  signal DDR_A_RD_DATA     : std_logic_vector(63 downto 0);
  signal DDR_A_RD_ADDR     : std_logic_vector(24 downto 0);
  signal DDR_A_RD_ADDR_WEN : std_logic;
  signal DDR_A_RD_ADDR_FF  : std_logic;
  signal DDR_A_RD_ADDR_AF  : std_logic;
  signal DDR_A_RD_RISE_REN : std_logic;
  signal DDR_A_RD_RISE_EF  : std_logic;
  signal DDR_A_RD_RISE_AE  : std_logic;
  signal DDR_A_RD_FALL_REN : std_logic;
  signal DDR_A_RD_FALL_EF  : std_logic;
  signal DDR_A_RD_FALL_AE  : std_logic;

  signal VCC               : std_logic;
  signal GND               : std_logic;

begin

  VCC <= '1';
  GND <= '0';

  -- RESET active low
  iRES : IBUF port map (I=>reset_pin, O=>xRESET);

  RESET <= NOT xRESET;

  -- UMIs
  iUMI0 : iobuf port map (T=>UMI_EN(0), I=>UMI_OUT(0), O=>UMI_IN(0), IO=>umi(0));
  iUMI1 : iobuf port map (T=>UMI_EN(1), I=>UMI_OUT(1), O=>UMI_IN(1), IO=>umi(1));
  iUMI2 : iobuf port map (T=>UMI_EN(2), I=>UMI_OUT(2), O=>UMI_IN(2), IO=>umi(2));
  iUMI3 : iobuf port map (T=>UMI_EN(3), I=>UMI_OUT(3), O=>UMI_IN(3), IO=>umi(3));

  -- Oscillator inputs
  iOSC0 : IBUF port map (I=>osc0_pin, O=>OSC0);
  iOSC3 : IBUF port map (I=>osc3_pin, O=>OSC3);

  -------------------------------------------------------------
  -- FIFO clocks

  iDICLK : IBUFG port map (I=>diclk, O=>xDICLK);
  oF1 : OBUF port map (I=>xF1, O=>f1);

  iDOCLK : IBUFG port map (I=>doclk, O=>xDOCLK);
  oF0 : OBUF port map (I=>xF0, O=>f0);

  -- same clock for both FIFO interfaces
  -- ===================================
  gFCKG : if (FCLK_G_DOMAIN) generate

    -- read clock
    -- ==========
    iGCLK : HE_RWCLK
      port map (
        DCLK => xDICLK,
        FCLK => xF1,
        --
        RST  => RESET,
        CLK  => SRC_FCLK_G,
        GCLK => xFCLK_G );

    -- write clock
    -- ===========
    xF0 <= SRC_FCLK_G;

    -- USER_AP clocks
    FCLK_RD <= xFCLK_G;
    FCLK_WR <= xFCLK_G;
    FCLK_G  <= xFCLK_G;

  end generate gFCKG;

  -- separate clocks for RD/WR FIFOs
  -- ===============================
  gNFCKG : if (NOT FCLK_G_DOMAIN) generate

    -- read clock
    -- ==========
    iRDCLK : HE_RWCLK
      port map (
        DCLK => xDICLK,
        FCLK => xF1,
        --
        RST  => RESET,
        CLK  => SRC_FCLK_RD,
        GCLK => FCLK_RD );

    -- write clock
    -- ===========
    iWRCLK : HE_RWCLK
      port map (
        DCLK => xDOCLK,
        FCLK => xF0,
        --
        RST  => RESET,
        CLK  => SRC_FCLK_WR,
        GCLK => FCLK_WR );

    -- unused clock
    FCLK_G  <= '0';

  end generate gNFCKG;

  -------------------------------------------------------------
  -- FIFO input

  iRD : HE_RD_6F
    port map (
      DIF_EF          => xDIF_EF,
      DIF_AE          => xDIF_AE,
      DIF_REN         => xDIF_REN,
      DIF_OEN         => xDIF_OEN,
      DI              => xDI,
      --
      RST             => RESET,
      CLK             => FCLK_RD,
      INFIFO_READ_REQ => INFIFO_READ_REQ,
      INFIFO_DVALID   => INFIFO_DVALID,
      INFIFO_SINGLE   => INFIFO_SINGLE,
      INFIFO_BURST    => INFIFO_BURST,
      INFIFO0_D       => INFIFO0_D,
      INFIFO1_D       => INFIFO1_D,
      INFIFO2_D       => INFIFO2_D,
      INFIFO3_D       => INFIFO3_D,
      INFIFO4_D       => INFIFO4_D,
      INFIFO5_D       => INFIFO5_D );

  iDI0  : IBUF port map (I=>di(0),  O=>xDI(0));
  iDI1  : IBUF port map (I=>di(1),  O=>xDI(1));
  iDI2  : IBUF port map (I=>di(2),  O=>xDI(2));
  iDI3  : IBUF port map (I=>di(3),  O=>xDI(3));
  iDI4  : IBUF port map (I=>di(4),  O=>xDI(4));
  iDI5  : IBUF port map (I=>di(5),  O=>xDI(5));
  iDI6  : IBUF port map (I=>di(6),  O=>xDI(6));
  iDI7  : IBUF port map (I=>di(7),  O=>xDI(7));

  iDI8  : IBUF port map (I=>di(8),  O=>xDI(8));
  iDI9  : IBUF port map (I=>di(9),  O=>xDI(9));
  iDI10 : IBUF port map (I=>di(10), O=>xDI(10));
  iDI11 : IBUF port map (I=>di(11), O=>xDI(11));
  iDI12 : IBUF port map (I=>di(12), O=>xDI(12));
  iDI13 : IBUF port map (I=>di(13), O=>xDI(13));
  iDI14 : IBUF port map (I=>di(14), O=>xDI(14));
  iDI15 : IBUF port map (I=>di(15), O=>xDI(15));

  iDI16 : IBUF port map (I=>di(16), O=>xDI(16));
  iDI17 : IBUF port map (I=>di(17), O=>xDI(17));
  iDI18 : IBUF port map (I=>di(18), O=>xDI(18));
  iDI19 : IBUF port map (I=>di(19), O=>xDI(19));
  iDI20 : IBUF port map (I=>di(20), O=>xDI(20));
  iDI21 : IBUF port map (I=>di(21), O=>xDI(21));
  iDI22 : IBUF port map (I=>di(22), O=>xDI(22));
  iDI23 : IBUF port map (I=>di(23), O=>xDI(23));

  iDI24 : IBUF port map (I=>di(24), O=>xDI(24));
  iDI25 : IBUF port map (I=>di(25), O=>xDI(25));
  iDI26 : IBUF port map (I=>di(26), O=>xDI(26));
  iDI27 : IBUF port map (I=>di(27), O=>xDI(27));
  iDI28 : IBUF port map (I=>di(28), O=>xDI(28));
  iDI29 : IBUF port map (I=>di(29), O=>xDI(29));
  iDI30 : IBUF port map (I=>di(30), O=>xDI(30));
  iDI31 : IBUF port map (I=>di(31), O=>xDI(31));

  iEF0 : IBUF port map (I=>dif_ef(0), O=>xDIF_EF(0));
  iEF1 : IBUF port map (I=>dif_ef(1), O=>xDIF_EF(1));
  iEF2 : IBUF port map (I=>dif_ef(2), O=>xDIF_EF(2));
  iEF3 : IBUF port map (I=>dif_ef(3), O=>xDIF_EF(3));
  iEF4 : IBUF port map (I=>dif_ef(4), O=>xDIF_EF(4));
  iEF5 : IBUF port map (I=>dif_ef(5), O=>xDIF_EF(5));

  iAE0 : IBUF port map (I=>dif_ae(0), O=>xDIF_AE(0));
  iAE1 : IBUF port map (I=>dif_ae(1), O=>xDIF_AE(1));
  iAE2 : IBUF port map (I=>dif_ae(2), O=>xDIF_AE(2));
  iAE3 : IBUF port map (I=>dif_ae(3), O=>xDIF_AE(3));
  iAE4 : IBUF port map (I=>dif_ae(4), O=>xDIF_AE(4));
  iAE5 : IBUF port map (I=>dif_ae(5), O=>xDIF_AE(5));

  oREN0 : OBUF port map (I=>xDIF_REN(0), O=>dif_ren(0));
  oREN1 : OBUF port map (I=>xDIF_REN(1), O=>dif_ren(1));
  oREN2 : OBUF port map (I=>xDIF_REN(2), O=>dif_ren(2));
  oREN3 : OBUF port map (I=>xDIF_REN(3), O=>dif_ren(3));
  oREN4 : OBUF port map (I=>xDIF_REN(4), O=>dif_ren(4));
  oREN5 : OBUF port map (I=>xDIF_REN(5), O=>dif_ren(5));

  oOEN0 : OBUF port map (I=>xDIF_OEN(0), O=>dif_oen(0));
  oOEN1 : OBUF port map (I=>xDIF_OEN(1), O=>dif_oen(1));
  oOEN2 : OBUF port map (I=>xDIF_OEN(2), O=>dif_oen(2));
  oOEN3 : OBUF port map (I=>xDIF_OEN(3), O=>dif_oen(3));
  oOEN4 : OBUF port map (I=>xDIF_OEN(4), O=>dif_oen(4));
  oOEN5 : OBUF port map (I=>xDIF_OEN(5), O=>dif_oen(5));

  -------------------------------------------------------------
  -- FIFO output

  iWR : HE_WR_6F
    port map (
      DOF_FF        => xDOF_FF,
      DOF_AF        => xDOF_AF,
      DOF_WEN       => xDOF_WEN,
      DO            => xDO,
      --
      RST           => RESET,
      CLK           => FCLK_WR,
      OUTFIFO_WRITE => OUTFIFO_WRITE,
      OUTFIFO_D     => OUTFIFO_D,
      OUTFIFO_READY => OUTFIFO_READY );

  oDO0  : OBUF port map (I=>xDO(0),  O=>do(0));
  oDO1  : OBUF port map (I=>xDO(1),  O=>do(1));
  oDO2  : OBUF port map (I=>xDO(2),  O=>do(2));
  oDO3  : OBUF port map (I=>xDO(3),  O=>do(3));
  oDO4  : OBUF port map (I=>xDO(4),  O=>do(4));
  oDO5  : OBUF port map (I=>xDO(5),  O=>do(5));
  oDO6  : OBUF port map (I=>xDO(6),  O=>do(6));
  oDO7  : OBUF port map (I=>xDO(7),  O=>do(7));

  oDO8  : OBUF port map (I=>xDO(8),  O=>do(8));
  oDO9  : OBUF port map (I=>xDO(9),  O=>do(9));
  oDO10 : OBUF port map (I=>xDO(10), O=>do(10));
  oDO11 : OBUF port map (I=>xDO(11), O=>do(11));
  oDO12 : OBUF port map (I=>xDO(12), O=>do(12));
  oDO13 : OBUF port map (I=>xDO(13), O=>do(13));
  oDO14 : OBUF port map (I=>xDO(14), O=>do(14));
  oDO15 : OBUF port map (I=>xDO(15), O=>do(15));

  oDO16 : OBUF port map (I=>xDO(16), O=>do(16));
  oDO17 : OBUF port map (I=>xDO(17), O=>do(17));
  oDO18 : OBUF port map (I=>xDO(18), O=>do(18));
  oDO19 : OBUF port map (I=>xDO(19), O=>do(19));
  oDO20 : OBUF port map (I=>xDO(20), O=>do(20));
  oDO21 : OBUF port map (I=>xDO(21), O=>do(21));
  oDO22 : OBUF port map (I=>xDO(22), O=>do(22));
  oDO23 : OBUF port map (I=>xDO(23), O=>do(23));

  oDO24 : OBUF port map (I=>xDO(24), O=>do(24));
  oDO25 : OBUF port map (I=>xDO(25), O=>do(25));
  oDO26 : OBUF port map (I=>xDO(26), O=>do(26));
  oDO27 : OBUF port map (I=>xDO(27), O=>do(27));
  oDO28 : OBUF port map (I=>xDO(28), O=>do(28));
  oDO29 : OBUF port map (I=>xDO(29), O=>do(29));
  oDO30 : OBUF port map (I=>xDO(30), O=>do(30));
  oDO31 : OBUF port map (I=>xDO(31), O=>do(31));

  iFF0 : IBUF port map (I=>dof_ff(0), O=>xDOF_FF(0));
  iFF1 : IBUF port map (I=>dof_ff(1), O=>xDOF_FF(1));
  iFF2 : IBUF port map (I=>dof_ff(2), O=>xDOF_FF(2));
  iFF3 : IBUF port map (I=>dof_ff(3), O=>xDOF_FF(3));
  iFF4 : IBUF port map (I=>dof_ff(4), O=>xDOF_FF(4));
  iFF5 : IBUF port map (I=>dof_ff(5), O=>xDOF_FF(5));

  iAF0 : IBUF port map (I=>dof_af(0), O=>xDOF_AF(0));
  iAF1 : IBUF port map (I=>dof_af(1), O=>xDOF_AF(1));
  iAF2 : IBUF port map (I=>dof_af(2), O=>xDOF_AF(2));
  iAF3 : IBUF port map (I=>dof_af(3), O=>xDOF_AF(3));
  iAF4 : IBUF port map (I=>dof_af(4), O=>xDOF_AF(4));
  iAF5 : IBUF port map (I=>dof_af(5), O=>xDOF_AF(5));

  oWEN0 : OBUF port map (I=>xDOF_WEN(0), O=>dof_wen(0));
  oWEN1 : OBUF port map (I=>xDOF_WEN(1), O=>dof_wen(1));
  oWEN2 : OBUF port map (I=>xDOF_WEN(2), O=>dof_wen(2));
  oWEN3 : OBUF port map (I=>xDOF_WEN(3), O=>dof_wen(3));
  oWEN4 : OBUF port map (I=>xDOF_WEN(4), O=>dof_wen(4));
  oWEN5 : OBUF port map (I=>xDOF_WEN(5), O=>dof_wen(5));

  -------------------------------------------------------------
  -- DDR SDRAM

  iDDR : HE_DDR
    port map (
      ddr_a_clk         => ddr_a_clk,
      ddr_a_clkb        => ddr_a_clkb,
      ddr_a_address     => ddr_a_address,
      ddr_a_BA          => ddr_a_BA,
      ddr_a_dq_in       => ddr_a_dq_in,
      ddr_a_dq_out      => ddr_a_dq_out,
      ddr_a_dq_en       => ddr_a_dq_en,
      ddr_a_dqs_in      => ddr_a_dqs_in,
      ddr_a_dqs_out     => ddr_a_dqs_out,
      ddr_a_dqs_en      => ddr_a_dqs_en,
      ddr_a_dm_out      => ddr_a_dm_out,
      ddr_a_dm_en       => ddr_a_dm_en,
      ddr_a_rasb        => ddr_a_rasb,
      ddr_a_casb        => ddr_a_casb,
      ddr_a_web         => ddr_a_web,
      --
      user_input_clk    => user_input_clk,
      user_rst          => RESET,
      --
      DDR_A_USER_CLK    => DDR_A_USER_CLK,
      --
      DDR_A_USER_RST    => DDR_A_USER_RST,
      --
      DDR_A_DATA_COUNT  => DDR_A_DATA_COUNT,
      --
      DDR_A_WR_DATA     => DDR_A_WR_DATA,
      DDR_A_WR_ADDR     => DDR_A_WR_ADDR,
      DDR_A_WR_ADDR_WEN => DDR_A_WR_ADDR_WEN,
      DDR_A_WR_ADDR_FF  => DDR_A_WR_ADDR_FF,
      DDR_A_WR_ADDR_AF  => DDR_A_WR_ADDR_AF,
      DDR_A_WR_RISE_WEN => DDR_A_WR_RISE_WEN,
      DDR_A_WR_RISE_FF  => DDR_A_WR_RISE_FF,
      DDR_A_WR_RISE_AF  => DDR_A_WR_RISE_AF,
      DDR_A_WR_FALL_WEN => DDR_A_WR_FALL_WEN,
      DDR_A_WR_FALL_FF  => DDR_A_WR_FALL_FF,
      DDR_A_WR_FALL_AF  => DDR_A_WR_FALL_AF,
      DDR_A_WR_DM_WEN   => DDR_A_WR_DM_WEN,
      DDR_A_WR_DM_FF    => DDR_A_WR_DM_FF,
      DDR_A_WR_DM_AF    => DDR_A_WR_DM_AF,
      --
      DDR_A_RD_DATA     => DDR_A_RD_DATA,
      DDR_A_RD_ADDR     => DDR_A_RD_ADDR,
      DDR_A_RD_ADDR_WEN => DDR_A_RD_ADDR_WEN,
      DDR_A_RD_ADDR_FF  => DDR_A_RD_ADDR_FF,
      DDR_A_RD_ADDR_AF  => DDR_A_RD_ADDR_AF,
      DDR_A_RD_RISE_REN => DDR_A_RD_RISE_REN,
      DDR_A_RD_RISE_EF  => DDR_A_RD_RISE_EF,
      DDR_A_RD_RISE_AE  => DDR_A_RD_RISE_AE,
      DDR_A_RD_FALL_REN => DDR_A_RD_FALL_REN,
      DDR_A_RD_FALL_EF  => DDR_A_RD_FALL_EF,
      DDR_A_RD_FALL_AE  => DDR_A_RD_FALL_AE );

  iSCLKI : IBUFG port map (I=>sdram_clkin, O=>user_input_clk);

  oSCLK_A0 : OBUF port map (I=>ddr_a_clk,  O=>sdram_a_clk_p);
  oSCLK_A1 : OBUF port map (I=>ddr_a_clkb, O=>sdram_a_clk_n);

  oSD_A_AD0  : OBUF port map (I=>ddr_a_address(0),  O=>sdram_a_a(0));
  oSD_A_AD1  : OBUF port map (I=>ddr_a_address(1),  O=>sdram_a_a(1));
  oSD_A_AD2  : OBUF port map (I=>ddr_a_address(2),  O=>sdram_a_a(2));
  oSD_A_AD3  : OBUF port map (I=>ddr_a_address(3),  O=>sdram_a_a(3));
  oSD_A_AD4  : OBUF port map (I=>ddr_a_address(4),  O=>sdram_a_a(4));
  oSD_A_AD5  : OBUF port map (I=>ddr_a_address(5),  O=>sdram_a_a(5));
  oSD_A_AD6  : OBUF port map (I=>ddr_a_address(6),  O=>sdram_a_a(6));
  oSD_A_AD7  : OBUF port map (I=>ddr_a_address(7),  O=>sdram_a_a(7));
  oSD_A_AD8  : OBUF port map (I=>ddr_a_address(8),  O=>sdram_a_a(8));
  oSD_A_AD9  : OBUF port map (I=>ddr_a_address(9),  O=>sdram_a_a(9));
  oSD_A_AD10 : OBUF port map (I=>ddr_a_address(10), O=>sdram_a_a(10));
  oSD_A_AD11 : OBUF port map (I=>ddr_a_address(11), O=>sdram_a_a(11));
  oSD_A_AD12 : OBUF port map (I=>ddr_a_address(12), O=>sdram_a_a(12));
  oSD_A_AD13 : OBUF port map (I=>ddr_a_address(13), O=>sdram_a_a(13));

  oSD_A_BA0 : OBUF port map (I=>ddr_a_BA(0), O=>sdram_a_ba(0));
  oSD_A_BA1 : OBUF port map (I=>ddr_a_BA(1), O=>sdram_a_ba(1));

  iSD_A_D0  : IOBUF port map (T=>ddr_a_dq_en(0),  I=>ddr_a_dq_out(0),  O=>ddr_a_dq_in(0),  IO=>sdram_a_dq(0));
  iSD_A_D1  : IOBUF port map (T=>ddr_a_dq_en(1),  I=>ddr_a_dq_out(1),  O=>ddr_a_dq_in(1),  IO=>sdram_a_dq(1));
  iSD_A_D2  : IOBUF port map (T=>ddr_a_dq_en(2),  I=>ddr_a_dq_out(2),  O=>ddr_a_dq_in(2),  IO=>sdram_a_dq(2));
  iSD_A_D3  : IOBUF port map (T=>ddr_a_dq_en(3),  I=>ddr_a_dq_out(3),  O=>ddr_a_dq_in(3),  IO=>sdram_a_dq(3));
  iSD_A_D4  : IOBUF port map (T=>ddr_a_dq_en(4),  I=>ddr_a_dq_out(4),  O=>ddr_a_dq_in(4),  IO=>sdram_a_dq(4));
  iSD_A_D5  : IOBUF port map (T=>ddr_a_dq_en(5),  I=>ddr_a_dq_out(5),  O=>ddr_a_dq_in(5),  IO=>sdram_a_dq(5));
  iSD_A_D6  : IOBUF port map (T=>ddr_a_dq_en(6),  I=>ddr_a_dq_out(6),  O=>ddr_a_dq_in(6),  IO=>sdram_a_dq(6));
  iSD_A_D7  : IOBUF port map (T=>ddr_a_dq_en(7),  I=>ddr_a_dq_out(7),  O=>ddr_a_dq_in(7),  IO=>sdram_a_dq(7));

  iSD_A_D8  : IOBUF port map (T=>ddr_a_dq_en(8),  I=>ddr_a_dq_out(8),  O=>ddr_a_dq_in(8),  IO=>sdram_a_dq(8));
  iSD_A_D9  : IOBUF port map (T=>ddr_a_dq_en(9),  I=>ddr_a_dq_out(9),  O=>ddr_a_dq_in(9),  IO=>sdram_a_dq(9));
  iSD_A_D10 : IOBUF port map (T=>ddr_a_dq_en(10), I=>ddr_a_dq_out(10), O=>ddr_a_dq_in(10), IO=>sdram_a_dq(10));
  iSD_A_D11 : IOBUF port map (T=>ddr_a_dq_en(11), I=>ddr_a_dq_out(11), O=>ddr_a_dq_in(11), IO=>sdram_a_dq(11));
  iSD_A_D12 : IOBUF port map (T=>ddr_a_dq_en(12), I=>ddr_a_dq_out(12), O=>ddr_a_dq_in(12), IO=>sdram_a_dq(12));
  iSD_A_D13 : IOBUF port map (T=>ddr_a_dq_en(13), I=>ddr_a_dq_out(13), O=>ddr_a_dq_in(13), IO=>sdram_a_dq(13));
  iSD_A_D14 : IOBUF port map (T=>ddr_a_dq_en(14), I=>ddr_a_dq_out(14), O=>ddr_a_dq_in(14), IO=>sdram_a_dq(14));
  iSD_A_D15 : IOBUF port map (T=>ddr_a_dq_en(15), I=>ddr_a_dq_out(15), O=>ddr_a_dq_in(15), IO=>sdram_a_dq(15));

  iSD_A_D16 : IOBUF port map (T=>ddr_a_dq_en(16), I=>ddr_a_dq_out(16), O=>ddr_a_dq_in(16), IO=>sdram_a_dq(16));
  iSD_A_D17 : IOBUF port map (T=>ddr_a_dq_en(17), I=>ddr_a_dq_out(17), O=>ddr_a_dq_in(17), IO=>sdram_a_dq(17));
  iSD_A_D18 : IOBUF port map (T=>ddr_a_dq_en(18), I=>ddr_a_dq_out(18), O=>ddr_a_dq_in(18), IO=>sdram_a_dq(18));
  iSD_A_D19 : IOBUF port map (T=>ddr_a_dq_en(19), I=>ddr_a_dq_out(19), O=>ddr_a_dq_in(19), IO=>sdram_a_dq(19));
  iSD_A_D20 : IOBUF port map (T=>ddr_a_dq_en(20), I=>ddr_a_dq_out(20), O=>ddr_a_dq_in(20), IO=>sdram_a_dq(20));
  iSD_A_D21 : IOBUF port map (T=>ddr_a_dq_en(21), I=>ddr_a_dq_out(21), O=>ddr_a_dq_in(21), IO=>sdram_a_dq(21));
  iSD_A_D22 : IOBUF port map (T=>ddr_a_dq_en(22), I=>ddr_a_dq_out(22), O=>ddr_a_dq_in(22), IO=>sdram_a_dq(22));
  iSD_A_D23 : IOBUF port map (T=>ddr_a_dq_en(23), I=>ddr_a_dq_out(23), O=>ddr_a_dq_in(23), IO=>sdram_a_dq(23));

  iSD_A_D24 : IOBUF port map (T=>ddr_a_dq_en(24), I=>ddr_a_dq_out(24), O=>ddr_a_dq_in(24), IO=>sdram_a_dq(24));
  iSD_A_D25 : IOBUF port map (T=>ddr_a_dq_en(25), I=>ddr_a_dq_out(25), O=>ddr_a_dq_in(25), IO=>sdram_a_dq(25));
  iSD_A_D26 : IOBUF port map (T=>ddr_a_dq_en(26), I=>ddr_a_dq_out(26), O=>ddr_a_dq_in(26), IO=>sdram_a_dq(26));
  iSD_A_D27 : IOBUF port map (T=>ddr_a_dq_en(27), I=>ddr_a_dq_out(27), O=>ddr_a_dq_in(27), IO=>sdram_a_dq(27));
  iSD_A_D28 : IOBUF port map (T=>ddr_a_dq_en(28), I=>ddr_a_dq_out(28), O=>ddr_a_dq_in(28), IO=>sdram_a_dq(28));
  iSD_A_D29 : IOBUF port map (T=>ddr_a_dq_en(29), I=>ddr_a_dq_out(29), O=>ddr_a_dq_in(29), IO=>sdram_a_dq(29));
  iSD_A_D30 : IOBUF port map (T=>ddr_a_dq_en(30), I=>ddr_a_dq_out(30), O=>ddr_a_dq_in(30), IO=>sdram_a_dq(30));
  iSD_A_D31 : IOBUF port map (T=>ddr_a_dq_en(31), I=>ddr_a_dq_out(31), O=>ddr_a_dq_in(31), IO=>sdram_a_dq(31));

  iSD_A_DQS0 : IOBUF port map (T=>ddr_a_dqs_en(0), I=>ddr_a_dqs_out(0), O=>ddr_a_dqs_in(0), IO=>sdram_a_dqs(0));
  iSD_A_DQS1 : IOBUF port map (T=>ddr_a_dqs_en(1), I=>ddr_a_dqs_out(1), O=>ddr_a_dqs_in(1), IO=>sdram_a_dqs(1));
  iSD_A_DQS2 : IOBUF port map (T=>ddr_a_dqs_en(2), I=>ddr_a_dqs_out(2), O=>ddr_a_dqs_in(2), IO=>sdram_a_dqs(2));
  iSD_A_DQS3 : IOBUF port map (T=>ddr_a_dqs_en(3), I=>ddr_a_dqs_out(3), O=>ddr_a_dqs_in(3), IO=>sdram_a_dqs(3));

  oSD_A_DM0 : OBUFT port map (I=>ddr_a_dm_out(0), T=>ddr_a_dm_en(0), O=>sdram_a_dm(0));
  oSD_A_DM1 : OBUFT port map (I=>ddr_a_dm_out(1), T=>ddr_a_dm_en(1), O=>sdram_a_dm(1));
  oSD_A_DM2 : OBUFT port map (I=>ddr_a_dm_out(2), T=>ddr_a_dm_en(2), O=>sdram_a_dm(2));
  oSD_A_DM3 : OBUFT port map (I=>ddr_a_dm_out(3), T=>ddr_a_dm_en(3), O=>sdram_a_dm(3));

  oSD_A_RAS : OBUF port map (I=>ddr_a_rasb, O=>sdram_a_ras);
  oSD_A_CAS : OBUF port map (I=>ddr_a_casb, O=>sdram_a_cas);
  oSD_A_WE  : OBUF port map (I=>ddr_a_web,  O=>sdram_a_we);

  -------------------------------------------------------------
  -- Serial Bus Interface

  iUSR : HE_USER
    port map (
      UADSTRB   => UADSTRB,
      UAD       => UAD,
      URDWR     => URDWR,
      UAD_IN    => UAD_IN,
      UAD_EN    => UAD_EN,
      UDONE     => UDONE,
      UAD_OUT   => UAD_OUT,
      --
      RST       => RESET,
      CLK       => MSG_CLK,
      MSG_READY => MSG_READY,
      MSG_DOUT  => MSG_DOUT,
      MSG_AEN   => MSG_AEN,
      MSG_WEN   => MSG_WEN,
      MSG_REN   => MSG_REN,
      MSG_ADDR  => MSG_ADDR,
      MSG_DIN   => MSG_DIN );

  iDONE   : obuf  port map (I=>UDONE, O=>done);

  iADSTRB : FDCP  port map (Q=>UADSTRB, C=>MSG_CLK, CLR=>GND, D=>adstrb, PRE=>RESET);

  iAD     : ibuf  port map (I=>ad,   O=>UAD  );
  iRDWR   : ibuf  port map (I=>rdwr, O=>URDWR);

  iAD0    : iobuf port map (T=>UAD_EN, I=>UAD_OUT(0), O=>UAD_IN(0), IO=>ad_bus(0));
  iAD1    : iobuf port map (T=>UAD_EN, I=>UAD_OUT(1), O=>UAD_IN(1), IO=>ad_bus(1));
  iAD2    : iobuf port map (T=>UAD_EN, I=>UAD_OUT(2), O=>UAD_IN(2), IO=>ad_bus(2));
  iAD3    : iobuf port map (T=>UAD_EN, I=>UAD_OUT(3), O=>UAD_IN(3), IO=>ad_bus(3));

  iMSTR : HE_MSG_MSTR
    port map (
      SFF           => SFF,
      SACK          => SACK,
      SCLK          => SCLK,
      SDAT          => SDAT,
      --
      RST           => RESET,
      CLK           => MSG_CLK,
      CID           => xCID,
      MID           => xMID(2 downto 0),
      MSG_SEND_MSG  => MSG_SEND_MSG,
      MSG_SEND_ID   => MSG_SEND_ID,
      MSG_LAST_BYTE => MSG_LAST_BYTE,
      MSG_DOUT      => MSG_DOUT,
      MSG_DONE      => MSG_DONE,
      MSG_COUNT     => MSG_COUNT,
      MSG_CLEAR     => MSG_CLEAR );

  iMFF  : FDCP port map (Q=>SFF,  C=>MSG_CLK, CLR=>GND, D=>mff,  PRE=>RESET);
  iMACK : FDCP port map (Q=>SACK, C=>MSG_CLK, CLR=>GND, D=>mack, PRE=>RESET);

  iMCLK : obuf port map (I=>SCLK, O=>mclk);
  iMDAT : obuf port map (I=>SDAT, O=>mdat);

  -------------------------------------------------------------
  -- Camera Link connections

  -- Camera Link Clock
  lvds_ibufg : IBUFGDS port map (I=>dio_a(16), IB=>dio_a(17), O=>CAM_CLK);

  -- Camera Link Data
  lvds_ibuf0 : IBUFDS port map (I=>dio_a(8),  IB=>dio_a(9),  O=>CAM_DATA(0));
  lvds_ibuf1 : IBUFDS port map (I=>dio_a(10), IB=>dio_a(11), O=>CAM_DATA(1));
  lvds_ibuf2 : IBUFDS port map (I=>dio_a(12), IB=>dio_a(13), O=>CAM_DATA(2));
  lvds_ibuf3 : IBUFDS port map (I=>dio_a(14), IB=>dio_a(15), O=>CAM_DATA(3));

  -- Camera Link Control
  lvds_obuf0  : OBUFDS port map (I=>CAM_CTRL(0), O=>dio_a(0), OB=>dio_a(1));
  lvds_obuf1  : OBUFDS port map (I=>CAM_CTRL(1), O=>dio_a(2), OB=>dio_a(3));
  lvds_obuf2  : OBUFDS port map (I=>CAM_CTRL(2), O=>dio_a(4), OB=>dio_a(5));
  lvds_obuf3  : OBUFDS port map (I=>CAM_CTRL(3), O=>dio_a(6), OB=>dio_a(7));

  -- Camera Link RS232 connection from HERON-FPGAx to camera
  lvds_obuf4  : OBUFDS port map (I=>CAM_SER_TC, O=>dio_a(18), OB=>dio_a(19));

  -- Camera Link RS232 connection from camera to HERON-FPGAx
  lvds_ibuf4  : IBUFDS port map (I=>dio_a(20), IB=>dio_a(21), O=>CAM_SER_TFG);

  -------------------------------------------------------------
  -- Connector Digital IO

  -- NOTE : Signals 0 to 21 on Connector A are used for Camera Link
  iDIOA22 : iobuf port map (T=>CONN_A_EN(22), I=>CONN_A_OUT(22), O=>CONN_A_IN(22), IO=>dio_a(22));
  iDIOA23 : iobuf port map (T=>CONN_A_EN(23), I=>CONN_A_OUT(23), O=>CONN_A_IN(23), IO=>dio_a(23));
  iDIOA24 : iobuf port map (T=>CONN_A_EN(24), I=>CONN_A_OUT(24), O=>CONN_A_IN(24), IO=>dio_a(24));
  iDIOA25 : iobuf port map (T=>CONN_A_EN(25), I=>CONN_A_OUT(25), O=>CONN_A_IN(25), IO=>dio_a(25));
  iDIOA26 : iobuf port map (T=>CONN_A_EN(26), I=>CONN_A_OUT(26), O=>CONN_A_IN(26), IO=>dio_a(26));
  iDIOA27 : iobuf port map (T=>CONN_A_EN(27), I=>CONN_A_OUT(27), O=>CONN_A_IN(27), IO=>dio_a(27));
  iDIOA28 : iobuf port map (T=>CONN_A_EN(28), I=>CONN_A_OUT(28), O=>CONN_A_IN(28), IO=>dio_a(28));
  iDIOA29 : iobuf port map (T=>CONN_A_EN(29), I=>CONN_A_OUT(29), O=>CONN_A_IN(29), IO=>dio_a(29));

  iDIOB0  : iobuf port map (T=>CONN_B_EN(0),  I=>CONN_B_OUT(0),  O=>CONN_B_IN(0),  IO=>dio_b(0) );
  iDIOB1  : iobuf port map (T=>CONN_B_EN(1),  I=>CONN_B_OUT(1),  O=>CONN_B_IN(1),  IO=>dio_b(1) );
  iDIOB2  : iobuf port map (T=>CONN_B_EN(2),  I=>CONN_B_OUT(2),  O=>CONN_B_IN(2),  IO=>dio_b(2) );
  iDIOB3  : iobuf port map (T=>CONN_B_EN(3),  I=>CONN_B_OUT(3),  O=>CONN_B_IN(3),  IO=>dio_b(3) );
  iDIOB4  : iobuf port map (T=>CONN_B_EN(4),  I=>CONN_B_OUT(4),  O=>CONN_B_IN(4),  IO=>dio_b(4) );
  iDIOB5  : iobuf port map (T=>CONN_B_EN(5),  I=>CONN_B_OUT(5),  O=>CONN_B_IN(5),  IO=>dio_b(5) );
  iDIOB6  : iobuf port map (T=>CONN_B_EN(6),  I=>CONN_B_OUT(6),  O=>CONN_B_IN(6),  IO=>dio_b(6) );
  iDIOB7  : iobuf port map (T=>CONN_B_EN(7),  I=>CONN_B_OUT(7),  O=>CONN_B_IN(7),  IO=>dio_b(7) );
  iDIOB8  : iobuf port map (T=>CONN_B_EN(8),  I=>CONN_B_OUT(8),  O=>CONN_B_IN(8),  IO=>dio_b(8) );
  iDIOB9  : iobuf port map (T=>CONN_B_EN(9),  I=>CONN_B_OUT(9),  O=>CONN_B_IN(9),  IO=>dio_b(9) );
  iDIOB10 : iobuf port map (T=>CONN_B_EN(10), I=>CONN_B_OUT(10), O=>CONN_B_IN(10), IO=>dio_b(10));
  iDIOB11 : iobuf port map (T=>CONN_B_EN(11), I=>CONN_B_OUT(11), O=>CONN_B_IN(11), IO=>dio_b(11));
  iDIOB12 : iobuf port map (T=>CONN_B_EN(12), I=>CONN_B_OUT(12), O=>CONN_B_IN(12), IO=>dio_b(12));
  iDIOB13 : iobuf port map (T=>CONN_B_EN(13), I=>CONN_B_OUT(13), O=>CONN_B_IN(13), IO=>dio_b(13));
  iDIOB14 : iobuf port map (T=>CONN_B_EN(14), I=>CONN_B_OUT(14), O=>CONN_B_IN(14), IO=>dio_b(14));
  iDIOB15 : iobuf port map (T=>CONN_B_EN(15), I=>CONN_B_OUT(15), O=>CONN_B_IN(15), IO=>dio_b(15));
  iDIOB16 : iobuf port map (T=>CONN_B_EN(16), I=>CONN_B_OUT(16), O=>CONN_B_IN(16), IO=>dio_b(16));
  iDIOB17 : iobuf port map (T=>CONN_B_EN(17), I=>CONN_B_OUT(17), O=>CONN_B_IN(17), IO=>dio_b(17));
  iDIOB18 : iobuf port map (T=>CONN_B_EN(18), I=>CONN_B_OUT(18), O=>CONN_B_IN(18), IO=>dio_b(18));
  iDIOB19 : iobuf port map (T=>CONN_B_EN(19), I=>CONN_B_OUT(19), O=>CONN_B_IN(19), IO=>dio_b(19));
  iDIOB20 : iobuf port map (T=>CONN_B_EN(20), I=>CONN_B_OUT(20), O=>CONN_B_IN(20), IO=>dio_b(20));
  iDIOB21 : iobuf port map (T=>CONN_B_EN(21), I=>CONN_B_OUT(21), O=>CONN_B_IN(21), IO=>dio_b(21));
  iDIOB22 : iobuf port map (T=>CONN_B_EN(22), I=>CONN_B_OUT(22), O=>CONN_B_IN(22), IO=>dio_b(22));
  iDIOB23 : iobuf port map (T=>CONN_B_EN(23), I=>CONN_B_OUT(23), O=>CONN_B_IN(23), IO=>dio_b(23));
  iDIOB24 : iobuf port map (T=>CONN_B_EN(24), I=>CONN_B_OUT(24), O=>CONN_B_IN(24), IO=>dio_b(24));
  iDIOB25 : iobuf port map (T=>CONN_B_EN(25), I=>CONN_B_OUT(25), O=>CONN_B_IN(25), IO=>dio_b(25));
  iDIOB26 : iobuf port map (T=>CONN_B_EN(26), I=>CONN_B_OUT(26), O=>CONN_B_IN(26), IO=>dio_b(26));
  iDIOB27 : iobuf port map (T=>CONN_B_EN(27), I=>CONN_B_OUT(27), O=>CONN_B_IN(27), IO=>dio_b(27));
  iDIOB28 : iobuf port map (T=>CONN_B_EN(28), I=>CONN_B_OUT(28), O=>CONN_B_IN(28), IO=>dio_b(28));
  iDIOB29 : iobuf port map (T=>CONN_B_EN(29), I=>CONN_B_OUT(29), O=>CONN_B_IN(29), IO=>dio_b(29));

  iDIOC0  : iobuf port map (T=>CONN_C_EN(0),  I=>CONN_C_OUT(0),  O=>CONN_C_IN(0),  IO=>dio_c(0) );
  iDIOC1  : iobuf port map (T=>CONN_C_EN(1),  I=>CONN_C_OUT(1),  O=>CONN_C_IN(1),  IO=>dio_c(1) );
  iDIOC2  : iobuf port map (T=>CONN_C_EN(2),  I=>CONN_C_OUT(2),  O=>CONN_C_IN(2),  IO=>dio_c(2) );
  iDIOC3  : iobuf port map (T=>CONN_C_EN(3),  I=>CONN_C_OUT(3),  O=>CONN_C_IN(3),  IO=>dio_c(3) );
  iDIOC4  : iobuf port map (T=>CONN_C_EN(4),  I=>CONN_C_OUT(4),  O=>CONN_C_IN(4),  IO=>dio_c(4) );
  iDIOC5  : iobuf port map (T=>CONN_C_EN(5),  I=>CONN_C_OUT(5),  O=>CONN_C_IN(5),  IO=>dio_c(5) );
  iDIOC6  : iobuf port map (T=>CONN_C_EN(6),  I=>CONN_C_OUT(6),  O=>CONN_C_IN(6),  IO=>dio_c(6) );
  iDIOC7  : iobuf port map (T=>CONN_C_EN(7),  I=>CONN_C_OUT(7),  O=>CONN_C_IN(7),  IO=>dio_c(7) );
  iDIOC8  : iobuf port map (T=>CONN_C_EN(8),  I=>CONN_C_OUT(8),  O=>CONN_C_IN(8),  IO=>dio_c(8) );
  iDIOC9  : iobuf port map (T=>CONN_C_EN(9),  I=>CONN_C_OUT(9),  O=>CONN_C_IN(9),  IO=>dio_c(9) );
  iDIOC10 : iobuf port map (T=>CONN_C_EN(10), I=>CONN_C_OUT(10), O=>CONN_C_IN(10), IO=>dio_c(10));
  iDIOC11 : iobuf port map (T=>CONN_C_EN(11), I=>CONN_C_OUT(11), O=>CONN_C_IN(11), IO=>dio_c(11));
  iDIOC12 : iobuf port map (T=>CONN_C_EN(12), I=>CONN_C_OUT(12), O=>CONN_C_IN(12), IO=>dio_c(12));
  iDIOC13 : iobuf port map (T=>CONN_C_EN(13), I=>CONN_C_OUT(13), O=>CONN_C_IN(13), IO=>dio_c(13));
  iDIOC14 : iobuf port map (T=>CONN_C_EN(14), I=>CONN_C_OUT(14), O=>CONN_C_IN(14), IO=>dio_c(14));
  iDIOC15 : iobuf port map (T=>CONN_C_EN(15), I=>CONN_C_OUT(15), O=>CONN_C_IN(15), IO=>dio_c(15));
  iDIOC16 : iobuf port map (T=>CONN_C_EN(16), I=>CONN_C_OUT(16), O=>CONN_C_IN(16), IO=>dio_c(16));
  iDIOC17 : iobuf port map (T=>CONN_C_EN(17), I=>CONN_C_OUT(17), O=>CONN_C_IN(17), IO=>dio_c(17));
  iDIOC18 : iobuf port map (T=>CONN_C_EN(18), I=>CONN_C_OUT(18), O=>CONN_C_IN(18), IO=>dio_c(18));
  iDIOC19 : iobuf port map (T=>CONN_C_EN(19), I=>CONN_C_OUT(19), O=>CONN_C_IN(19), IO=>dio_c(19));
  iDIOC20 : iobuf port map (T=>CONN_C_EN(20), I=>CONN_C_OUT(20), O=>CONN_C_IN(20), IO=>dio_c(20));
  iDIOC21 : iobuf port map (T=>CONN_C_EN(21), I=>CONN_C_OUT(21), O=>CONN_C_IN(21), IO=>dio_c(21));
  iDIOC22 : iobuf port map (T=>CONN_C_EN(22), I=>CONN_C_OUT(22), O=>CONN_C_IN(22), IO=>dio_c(22));
  iDIOC23 : iobuf port map (T=>CONN_C_EN(23), I=>CONN_C_OUT(23), O=>CONN_C_IN(23), IO=>dio_c(23));
  iDIOC24 : iobuf port map (T=>CONN_C_EN(24), I=>CONN_C_OUT(24), O=>CONN_C_IN(24), IO=>dio_c(24));
  iDIOC25 : iobuf port map (T=>CONN_C_EN(25), I=>CONN_C_OUT(25), O=>CONN_C_IN(25), IO=>dio_c(25));
  iDIOC26 : iobuf port map (T=>CONN_C_EN(26), I=>CONN_C_OUT(26), O=>CONN_C_IN(26), IO=>dio_c(26));
  iDIOC27 : iobuf port map (T=>CONN_C_EN(27), I=>CONN_C_OUT(27), O=>CONN_C_IN(27), IO=>dio_c(27));
  iDIOC28 : iobuf port map (T=>CONN_C_EN(28), I=>CONN_C_OUT(28), O=>CONN_C_IN(28), IO=>dio_c(28));
  iDIOC29 : iobuf port map (T=>CONN_C_EN(29), I=>CONN_C_OUT(29), O=>CONN_C_IN(29), IO=>dio_c(29));

  iDIOD0  : iobuf port map (T=>CONN_D_EN(0),  I=>CONN_D_OUT(0),  O=>CONN_D_IN(0),  IO=>dio_d(0) );
  iDIOD1  : iobuf port map (T=>CONN_D_EN(1),  I=>CONN_D_OUT(1),  O=>CONN_D_IN(1),  IO=>dio_d(1) );
  iDIOD2  : iobuf port map (T=>CONN_D_EN(2),  I=>CONN_D_OUT(2),  O=>CONN_D_IN(2),  IO=>dio_d(2) );
  iDIOD3  : iobuf port map (T=>CONN_D_EN(3),  I=>CONN_D_OUT(3),  O=>CONN_D_IN(3),  IO=>dio_d(3) );
  iDIOD4  : iobuf port map (T=>CONN_D_EN(4),  I=>CONN_D_OUT(4),  O=>CONN_D_IN(4),  IO=>dio_d(4) );
  iDIOD5  : iobuf port map (T=>CONN_D_EN(5),  I=>CONN_D_OUT(5),  O=>CONN_D_IN(5),  IO=>dio_d(5) );
  iDIOD6  : iobuf port map (T=>CONN_D_EN(6),  I=>CONN_D_OUT(6),  O=>CONN_D_IN(6),  IO=>dio_d(6) );
  iDIOD7  : iobuf port map (T=>CONN_D_EN(7),  I=>CONN_D_OUT(7),  O=>CONN_D_IN(7),  IO=>dio_d(7) );
  iDIOD8  : iobuf port map (T=>CONN_D_EN(8),  I=>CONN_D_OUT(8),  O=>CONN_D_IN(8),  IO=>dio_d(8) );
  iDIOD9  : iobuf port map (T=>CONN_D_EN(9),  I=>CONN_D_OUT(9),  O=>CONN_D_IN(9),  IO=>dio_d(9) );
  iDIOD10 : iobuf port map (T=>CONN_D_EN(10), I=>CONN_D_OUT(10), O=>CONN_D_IN(10), IO=>dio_d(10));
  iDIOD11 : iobuf port map (T=>CONN_D_EN(11), I=>CONN_D_OUT(11), O=>CONN_D_IN(11), IO=>dio_d(11));
  iDIOD12 : iobuf port map (T=>CONN_D_EN(12), I=>CONN_D_OUT(12), O=>CONN_D_IN(12), IO=>dio_d(12));
  iDIOD13 : iobuf port map (T=>CONN_D_EN(13), I=>CONN_D_OUT(13), O=>CONN_D_IN(13), IO=>dio_d(13));
  iDIOD14 : iobuf port map (T=>CONN_D_EN(14), I=>CONN_D_OUT(14), O=>CONN_D_IN(14), IO=>dio_d(14));
  iDIOD15 : iobuf port map (T=>CONN_D_EN(15), I=>CONN_D_OUT(15), O=>CONN_D_IN(15), IO=>dio_d(15));
  iDIOD16 : iobuf port map (T=>CONN_D_EN(16), I=>CONN_D_OUT(16), O=>CONN_D_IN(16), IO=>dio_d(16));
  iDIOD17 : iobuf port map (T=>CONN_D_EN(17), I=>CONN_D_OUT(17), O=>CONN_D_IN(17), IO=>dio_d(17));
  iDIOD18 : iobuf port map (T=>CONN_D_EN(18), I=>CONN_D_OUT(18), O=>CONN_D_IN(18), IO=>dio_d(18));
  iDIOD19 : iobuf port map (T=>CONN_D_EN(19), I=>CONN_D_OUT(19), O=>CONN_D_IN(19), IO=>dio_d(19));
  iDIOD20 : iobuf port map (T=>CONN_D_EN(20), I=>CONN_D_OUT(20), O=>CONN_D_IN(20), IO=>dio_d(20));
  iDIOD21 : iobuf port map (T=>CONN_D_EN(21), I=>CONN_D_OUT(21), O=>CONN_D_IN(21), IO=>dio_d(21));
  iDIOD22 : iobuf port map (T=>CONN_D_EN(22), I=>CONN_D_OUT(22), O=>CONN_D_IN(22), IO=>dio_d(22));
  iDIOD23 : iobuf port map (T=>CONN_D_EN(23), I=>CONN_D_OUT(23), O=>CONN_D_IN(23), IO=>dio_d(23));
  iDIOD24 : iobuf port map (T=>CONN_D_EN(24), I=>CONN_D_OUT(24), O=>CONN_D_IN(24), IO=>dio_d(24));
  iDIOD25 : iobuf port map (T=>CONN_D_EN(25), I=>CONN_D_OUT(25), O=>CONN_D_IN(25), IO=>dio_d(25));
  iDIOD26 : iobuf port map (T=>CONN_D_EN(26), I=>CONN_D_OUT(26), O=>CONN_D_IN(26), IO=>dio_d(26));
  iDIOD27 : iobuf port map (T=>CONN_D_EN(27), I=>CONN_D_OUT(27), O=>CONN_D_IN(27), IO=>dio_d(27));
  iDIOD28 : iobuf port map (T=>CONN_D_EN(28), I=>CONN_D_OUT(28), O=>CONN_D_IN(28), IO=>dio_d(28));
  iDIOD29 : iobuf port map (T=>CONN_D_EN(29), I=>CONN_D_OUT(29), O=>CONN_D_IN(29), IO=>dio_d(29));

  iDIOE0  : iobuf port map (T=>CONN_E_EN(0),  I=>CONN_E_OUT(0),  O=>CONN_E_IN(0),  IO=>dio_e(0) );
  iDIOE1  : iobuf port map (T=>CONN_E_EN(1),  I=>CONN_E_OUT(1),  O=>CONN_E_IN(1),  IO=>dio_e(1) );
  iDIOE2  : iobuf port map (T=>CONN_E_EN(2),  I=>CONN_E_OUT(2),  O=>CONN_E_IN(2),  IO=>dio_e(2) );
  iDIOE3  : iobuf port map (T=>CONN_E_EN(3),  I=>CONN_E_OUT(3),  O=>CONN_E_IN(3),  IO=>dio_e(3) );
  iDIOE4  : iobuf port map (T=>CONN_E_EN(4),  I=>CONN_E_OUT(4),  O=>CONN_E_IN(4),  IO=>dio_e(4) );
  iDIOE5  : iobuf port map (T=>CONN_E_EN(5),  I=>CONN_E_OUT(5),  O=>CONN_E_IN(5),  IO=>dio_e(5) );
  iDIOE6  : iobuf port map (T=>CONN_E_EN(6),  I=>CONN_E_OUT(6),  O=>CONN_E_IN(6),  IO=>dio_e(6) );
  iDIOE7  : iobuf port map (T=>CONN_E_EN(7),  I=>CONN_E_OUT(7),  O=>CONN_E_IN(7),  IO=>dio_e(7) );
  iDIOE8  : iobuf port map (T=>CONN_E_EN(8),  I=>CONN_E_OUT(8),  O=>CONN_E_IN(8),  IO=>dio_e(8) );
  iDIOE9  : iobuf port map (T=>CONN_E_EN(9),  I=>CONN_E_OUT(9),  O=>CONN_E_IN(9),  IO=>dio_e(9) );
  iDIOE10 : iobuf port map (T=>CONN_E_EN(10), I=>CONN_E_OUT(10), O=>CONN_E_IN(10), IO=>dio_e(10));
  iDIOE11 : iobuf port map (T=>CONN_E_EN(11), I=>CONN_E_OUT(11), O=>CONN_E_IN(11), IO=>dio_e(11));
  iDIOE12 : iobuf port map (T=>CONN_E_EN(12), I=>CONN_E_OUT(12), O=>CONN_E_IN(12), IO=>dio_e(12));
  iDIOE13 : iobuf port map (T=>CONN_E_EN(13), I=>CONN_E_OUT(13), O=>CONN_E_IN(13), IO=>dio_e(13));
  iDIOE14 : iobuf port map (T=>CONN_E_EN(14), I=>CONN_E_OUT(14), O=>CONN_E_IN(14), IO=>dio_e(14));
  iDIOE15 : iobuf port map (T=>CONN_E_EN(15), I=>CONN_E_OUT(15), O=>CONN_E_IN(15), IO=>dio_e(15));
  iDIOE16 : iobuf port map (T=>CONN_E_EN(16), I=>CONN_E_OUT(16), O=>CONN_E_IN(16), IO=>dio_e(16));
  iDIOE17 : iobuf port map (T=>CONN_E_EN(17), I=>CONN_E_OUT(17), O=>CONN_E_IN(17), IO=>dio_e(17));
  iDIOE18 : iobuf port map (T=>CONN_E_EN(18), I=>CONN_E_OUT(18), O=>CONN_E_IN(18), IO=>dio_e(18));
  iDIOE19 : iobuf port map (T=>CONN_E_EN(19), I=>CONN_E_OUT(19), O=>CONN_E_IN(19), IO=>dio_e(19));
  iDIOE20 : iobuf port map (T=>CONN_E_EN(20), I=>CONN_E_OUT(20), O=>CONN_E_IN(20), IO=>dio_e(20));
  iDIOE21 : iobuf port map (T=>CONN_E_EN(21), I=>CONN_E_OUT(21), O=>CONN_E_IN(21), IO=>dio_e(21));
  iDIOE22 : iobuf port map (T=>CONN_E_EN(22), I=>CONN_E_OUT(22), O=>CONN_E_IN(22), IO=>dio_e(22));
  iDIOE23 : iobuf port map (T=>CONN_E_EN(23), I=>CONN_E_OUT(23), O=>CONN_E_IN(23), IO=>dio_e(23));
  iDIOE24 : iobuf port map (T=>CONN_E_EN(24), I=>CONN_E_OUT(24), O=>CONN_E_IN(24), IO=>dio_e(24));
  iDIOE25 : iobuf port map (T=>CONN_E_EN(25), I=>CONN_E_OUT(25), O=>CONN_E_IN(25), IO=>dio_e(25));
  iDIOE26 : iobuf port map (T=>CONN_E_EN(26), I=>CONN_E_OUT(26), O=>CONN_E_IN(26), IO=>dio_e(26));
  iDIOE27 : iobuf port map (T=>CONN_E_EN(27), I=>CONN_E_OUT(27), O=>CONN_E_IN(27), IO=>dio_e(27));
  iDIOE28 : iobuf port map (T=>CONN_E_EN(28), I=>CONN_E_OUT(28), O=>CONN_E_IN(28), IO=>dio_e(28));
  iDIOE29 : iobuf port map (T=>CONN_E_EN(29), I=>CONN_E_OUT(29), O=>CONN_E_IN(29), IO=>dio_e(29));

  iDIOF0  : iobuf port map (T=>CONN_F_EN(0),  I=>CONN_F_OUT(0),  O=>CONN_F_IN(0),  IO=>dio_f(0) );
  iDIOF1  : iobuf port map (T=>CONN_F_EN(1),  I=>CONN_F_OUT(1),  O=>CONN_F_IN(1),  IO=>dio_f(1) );
  iDIOF2  : iobuf port map (T=>CONN_F_EN(2),  I=>CONN_F_OUT(2),  O=>CONN_F_IN(2),  IO=>dio_f(2) );
  iDIOF3  : iobuf port map (T=>CONN_F_EN(3),  I=>CONN_F_OUT(3),  O=>CONN_F_IN(3),  IO=>dio_f(3) );
  iDIOF4  : iobuf port map (T=>CONN_F_EN(4),  I=>CONN_F_OUT(4),  O=>CONN_F_IN(4),  IO=>dio_f(4) );
  iDIOF5  : iobuf port map (T=>CONN_F_EN(5),  I=>CONN_F_OUT(5),  O=>CONN_F_IN(5),  IO=>dio_f(5) );
  iDIOF6  : iobuf port map (T=>CONN_F_EN(6),  I=>CONN_F_OUT(6),  O=>CONN_F_IN(6),  IO=>dio_f(6) );
  iDIOF7  : iobuf port map (T=>CONN_F_EN(7),  I=>CONN_F_OUT(7),  O=>CONN_F_IN(7),  IO=>dio_f(7) );
  iDIOF8  : iobuf port map (T=>CONN_F_EN(8),  I=>CONN_F_OUT(8),  O=>CONN_F_IN(8),  IO=>dio_f(8) );
  iDIOF9  : iobuf port map (T=>CONN_F_EN(9),  I=>CONN_F_OUT(9),  O=>CONN_F_IN(9),  IO=>dio_f(9) );
  iDIOF10 : iobuf port map (T=>CONN_F_EN(10), I=>CONN_F_OUT(10), O=>CONN_F_IN(10), IO=>dio_f(10));
  iDIOF11 : iobuf port map (T=>CONN_F_EN(11), I=>CONN_F_OUT(11), O=>CONN_F_IN(11), IO=>dio_f(11));
  iDIOF12 : iobuf port map (T=>CONN_F_EN(12), I=>CONN_F_OUT(12), O=>CONN_F_IN(12), IO=>dio_f(12));
  iDIOF13 : iobuf port map (T=>CONN_F_EN(13), I=>CONN_F_OUT(13), O=>CONN_F_IN(13), IO=>dio_f(13));
  iDIOF14 : iobuf port map (T=>CONN_F_EN(14), I=>CONN_F_OUT(14), O=>CONN_F_IN(14), IO=>dio_f(14));
  iDIOF15 : iobuf port map (T=>CONN_F_EN(15), I=>CONN_F_OUT(15), O=>CONN_F_IN(15), IO=>dio_f(15));
  iDIOF16 : iobuf port map (T=>CONN_F_EN(16), I=>CONN_F_OUT(16), O=>CONN_F_IN(16), IO=>dio_f(16));
  iDIOF17 : iobuf port map (T=>CONN_F_EN(17), I=>CONN_F_OUT(17), O=>CONN_F_IN(17), IO=>dio_f(17));
  iDIOF18 : iobuf port map (T=>CONN_F_EN(18), I=>CONN_F_OUT(18), O=>CONN_F_IN(18), IO=>dio_f(18));
  iDIOF19 : iobuf port map (T=>CONN_F_EN(19), I=>CONN_F_OUT(19), O=>CONN_F_IN(19), IO=>dio_f(19));
  iDIOF20 : iobuf port map (T=>CONN_F_EN(20), I=>CONN_F_OUT(20), O=>CONN_F_IN(20), IO=>dio_f(20));
  iDIOF21 : iobuf port map (T=>CONN_F_EN(21), I=>CONN_F_OUT(21), O=>CONN_F_IN(21), IO=>dio_f(21));
  iDIOF22 : iobuf port map (T=>CONN_F_EN(22), I=>CONN_F_OUT(22), O=>CONN_F_IN(22), IO=>dio_f(22));
  iDIOF23 : iobuf port map (T=>CONN_F_EN(23), I=>CONN_F_OUT(23), O=>CONN_F_IN(23), IO=>dio_f(23));
  iDIOF24 : iobuf port map (T=>CONN_F_EN(24), I=>CONN_F_OUT(24), O=>CONN_F_IN(24), IO=>dio_f(24));
  iDIOF25 : iobuf port map (T=>CONN_F_EN(25), I=>CONN_F_OUT(25), O=>CONN_F_IN(25), IO=>dio_f(25));
  iDIOF26 : iobuf port map (T=>CONN_F_EN(26), I=>CONN_F_OUT(26), O=>CONN_F_IN(26), IO=>dio_f(26));
  iDIOF27 : iobuf port map (T=>CONN_F_EN(27), I=>CONN_F_OUT(27), O=>CONN_F_IN(27), IO=>dio_f(27));
  iDIOF28 : iobuf port map (T=>CONN_F_EN(28), I=>CONN_F_OUT(28), O=>CONN_F_IN(28), IO=>dio_f(28));
  iDIOF29 : iobuf port map (T=>CONN_F_EN(29), I=>CONN_F_OUT(29), O=>CONN_F_IN(29), IO=>dio_f(29));

  -------------------------------------------------------------
  -- USER_AP

  iuser_ap : USER_AP
    port map (
      RESET             => RESET,
      CONFIG            => xCONFIG,
      --
      OSC0              => OSC0,
      OSC3              => OSC3,
      --
      UDPRES            => xUDPRES,
      LED               => xLED,
      --
      MOD_HAS_PROC      => xMOD_HAS_PROC,
      --
      CID               => xCID,
      MID               => xMID,
      UMI_IN            => UMI_IN,
      UMI_OUT           => UMI_OUT,
      UMI_EN            => UMI_EN,
      --
      FCLK_RD           => FCLK_RD,
      SRC_FCLK_RD       => SRC_FCLK_RD,
      --
      FCLK_WR           => FCLK_WR,
      SRC_FCLK_WR       => SRC_FCLK_WR,
      --
      FCLK_G            => FCLK_G,
      SRC_FCLK_G        => SRC_FCLK_G,
      --
      INFIFO_READ_REQ   => INFIFO_READ_REQ,
      INFIFO_DVALID     => INFIFO_DVALID,
      INFIFO_SINGLE     => INFIFO_SINGLE,
      INFIFO_BURST      => INFIFO_BURST,
      INFIFO0_D         => INFIFO0_D,
      INFIFO1_D         => INFIFO1_D,
      INFIFO2_D         => INFIFO2_D,
      INFIFO3_D         => INFIFO3_D,
      INFIFO4_D         => INFIFO4_D,
      INFIFO5_D         => INFIFO5_D,
      --
      OUTFIFO_READY     => OUTFIFO_READY,
      OUTFIFO_WRITE     => OUTFIFO_WRITE,
      OUTFIFO_D         => OUTFIFO_D,
      --
      MSG_CLK           => MSG_CLK,
      MSG_DIN           => MSG_DIN,
      MSG_ADDR          => MSG_ADDR,
      MSG_AEN           => MSG_AEN,
      MSG_WEN           => MSG_WEN,
      MSG_REN           => MSG_REN,
      MSG_DONE          => MSG_DONE,
      MSG_COUNT         => MSG_COUNT,
      MSG_CLEAR         => MSG_CLEAR,
      MSG_READY         => MSG_READY,
      MSG_SEND_MSG      => MSG_SEND_MSG,
      MSG_CE            => MSG_CE,
      MSG_DOUT          => MSG_DOUT,
      MSG_SEND_ID       => MSG_SEND_ID,
      MSG_LAST_BYTE     => MSG_LAST_BYTE,
      --
      CAM_CLK           => CAM_CLK,
      CAM_DATA          => CAM_DATA,
      CAM_CTRL          => CAM_CTRL,
      CAM_SER_TC        => CAM_SER_TC,
      CAM_SER_TFG       => CAM_SER_TFG,
      --
      CONN_A_IN         => CONN_A_IN,
      CONN_A_OUT        => CONN_A_OUT,
      CONN_A_EN         => CONN_A_EN,
      CONN_B_IN         => CONN_B_IN,
      CONN_B_OUT        => CONN_B_OUT,
      CONN_B_EN         => CONN_B_EN,
      CONN_C_IN         => CONN_C_IN,
      CONN_C_OUT        => CONN_C_OUT,
      CONN_C_EN         => CONN_C_EN,
      CONN_D_IN         => CONN_D_IN,
      CONN_D_OUT        => CONN_D_OUT,
      CONN_D_EN         => CONN_D_EN,
      CONN_E_IN         => CONN_E_IN,
      CONN_E_OUT        => CONN_E_OUT,
      CONN_E_EN         => CONN_E_EN,
      CONN_F_IN         => CONN_F_IN,
      CONN_F_OUT        => CONN_F_OUT,
      CONN_F_EN         => CONN_F_EN,
      --
      DDR_A_USER_CLK    => DDR_A_USER_CLK,
      --
      DDR_A_USER_RST    => DDR_A_USER_RST,
      --
      DDR_A_DATA_COUNT  => DDR_A_DATA_COUNT,
      --
      DDR_A_WR_DATA     => DDR_A_WR_DATA,
      DDR_A_WR_ADDR     => DDR_A_WR_ADDR,
      DDR_A_WR_ADDR_WEN => DDR_A_WR_ADDR_WEN,
      DDR_A_WR_ADDR_FF  => DDR_A_WR_ADDR_FF,
      DDR_A_WR_ADDR_AF  => DDR_A_WR_ADDR_AF,
      DDR_A_WR_RISE_WEN => DDR_A_WR_RISE_WEN,
      DDR_A_WR_RISE_FF  => DDR_A_WR_RISE_FF,
      DDR_A_WR_RISE_AF  => DDR_A_WR_RISE_AF,
      DDR_A_WR_FALL_WEN => DDR_A_WR_FALL_WEN,
      DDR_A_WR_FALL_FF  => DDR_A_WR_FALL_FF,
      DDR_A_WR_FALL_AF  => DDR_A_WR_FALL_AF,
      DDR_A_WR_DM_WEN   => DDR_A_WR_DM_WEN,
      DDR_A_WR_DM_FF    => DDR_A_WR_DM_FF,
      DDR_A_WR_DM_AF    => DDR_A_WR_DM_AF,
      --
      DDR_A_RD_DATA     => DDR_A_RD_DATA,
      DDR_A_RD_ADDR     => DDR_A_RD_ADDR,
      DDR_A_RD_ADDR_WEN => DDR_A_RD_ADDR_WEN,
      DDR_A_RD_ADDR_FF  => DDR_A_RD_ADDR_FF,
      DDR_A_RD_ADDR_AF  => DDR_A_RD_ADDR_AF,
      DDR_A_RD_RISE_REN => DDR_A_RD_RISE_REN,
      DDR_A_RD_RISE_EF  => DDR_A_RD_RISE_EF,
      DDR_A_RD_RISE_AE  => DDR_A_RD_RISE_AE,
      DDR_A_RD_FALL_REN => DDR_A_RD_FALL_REN,
      DDR_A_RD_FALL_EF  => DDR_A_RD_FALL_EF,
      DDR_A_RD_FALL_AE  => DDR_A_RD_FALL_AE );

  iCFG : IBUF port map (I=>config, O=>xCONFIG);

  oUDP : OBUF port map (I=>xUDPRES, O=>udpres);

  oLED0 : OBUF port map (I=>xLED(0), O=>led(0));
  oLED1 : OBUF port map (I=>xLED(1), O=>led(1));
  oLED2 : OBUF port map (I=>xLED(2), O=>led(2));
  oLED3 : OBUF port map (I=>xLED(3), O=>led(3));
  oLED4 : OBUF port map (I=>xLED(4), O=>led(4));

  iAFS : OBUF port map (I=>xMOD_HAS_PROC, O=>module_has_proc);

  iCID0 : IBUF port map (I=>cid(0), O=>xCID(0));
  iCID1 : IBUF port map (I=>cid(1), O=>xCID(1));
  iCID2 : IBUF port map (I=>cid(2), O=>xCID(2));
  iCID3 : IBUF port map (I=>cid(3), O=>xCID(3));

  iMID0 : IBUF port map (I=>mid(0), O=>xMID(0));
  iMID1 : IBUF port map (I=>mid(1), O=>xMID(1));
  iMID2 : IBUF port map (I=>mid(2), O=>xMID(2));
  iMID3 : IBUF port map (I=>mid(3), O=>xMID(3));

end RTL;
