-- ==============================================================
-- FILE : HSB2.VHD  -  may be modified by the USER
-- ==============================================================
--
-- This file is part of Example 2, for the HERON-FPGA14 module.
--
-- This file may be modified by the users to implement their
-- own logic.
--
-- ==============================================================
--
--  Module      : HSB2
--  Date        : 06/04/2006
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : HUNT Message Interface
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    06-04-06    Taken from FPGA12 Example 2.
--
-- ==============================================================


library IEEE;
  use IEEE.std_logic_1164.all;

entity HSB2 is
  port (
    RST          : in  std_logic;
    CLK          : in  std_logic;
    DIN          : in  std_logic_vector(7 downto 0);
    ADDR         : in  std_logic_vector(7 downto 0);
    AEN          : in  std_logic;
    WEN          : in  std_logic;
    REN          : in  std_logic;
    DONE         : in  std_logic;
    COUNT        : in  std_logic;
    CLEAR        : in  std_logic;
    READY        : out std_logic;
    SEND_MSG     : out std_logic;
    CE           : out std_logic;
    DOUT         : out std_logic_vector(7 downto 0);
    SEND_ID      : out std_logic;
    LAST_BYTE    : out std_logic
  );
end HSB2;


architecture RTL of HSB2 is

begin

  SEND_MSG  <= '0';
  CE        <= '0';
  SEND_ID   <= '0';
  LAST_BYTE <= '0';

  DOUT      <= (others=>'0');

  -- READY
  process (RST, CLK)
  begin
    if RST='1' then
      READY <= '1';
    elsif rising_edge(CLK) then
      READY <= WEN OR REN;
    end if;
  end process;

end RTL;
