-- ==============================================================
-- FILE : USER_AP1.VHD  -  MUST be modified by the USER
-- ==============================================================
--
-- This file is part of Example 1, for the HERON-FPGA14 module.
--
-- This file must be modified by the user.
--
-- ==============================================================
--
--  Date        : 06/04/2006
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : User code section
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    06-04-06    Taken from FPGA12 Example 1.
--
-- ==============================================================



-- ==============================================================
--   Package : CONFIG
-- ==============================================================
--
-- This package allow users to set up the different clock domains
-- of the application (FIFO interfaces) in the top level.
-- Please refer to the HUNT documentation for more details.
--
-- ==============================================================

package CONFIG is

  -- FIFO CLOCK
  -- ==========

--   --------------------------------------------------------------------
--   Normally you will use the same clock source for the input and output
--   HERON FIFOs. In that case you need a single clock domain.
--   Then you drive SRC_FCLK_G with the frequency you want, which for the 
--   HEPC9/HECPCI9/HERON_BASE2 must be >=60Mhz and <= 100Mhz.
--   The clock you use in your design is then FCLK_G which has the corrct 
--   phase relative to the FIFO data.
--   In this case set FCLK_G_DOMAIN = TRUE

--   If however you want to use different clocks for the input and output 
--   HERON FIFOs, you have seperate clock domains.
--   Now you drive the signals SRC_FCLK_RD and SRC_FCLK_WR with the frequencies
--   you want, (still probably >60Mhz and <100Mhz) and your design must use 
--   FCLK_RD to deal with input FIFO data but FCLK_WR to deal with output FIFO data.
--   In this case set FCLK_G_DOMAIN = FALSE

  -- To use a single common FIFO clock, set FCLK_G_DOMAIN = TRUE
  constant FCLK_G_DOMAIN : boolean := TRUE;

end CONFIG;


-- ==============================================================
--   Module : USER_AP
-- ==============================================================

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.numeric_std.all;
  use WORK.CONFIG.all;


--pragma translate_off
library sim_lib;
  use sim_lib.all;

library UNISIM;
  use UNISIM.VCOMPONENTS.all;
--pragma translate_on


entity USER_AP is
  port (
    RESET             : in  std_logic;                      -- Asynchronous reset active high
    CONFIG            : in  std_logic;                      -- System wide Config signal
-- CLOCK IO
    OSC0              : in  std_logic;                      -- Xtal OSC0
    OSC3              : in  std_logic;                      -- Xtal OSC3 factory default fitted with 100Mhz
-- MISCELLANEOUS IO
    UDPRES            : out std_logic;                      -- reset the carrier (high if NOT used)
    LED               : out std_logic_vector(4 downto 0);   -- LEDs
    MOD_HAS_PROC      : out std_logic;
    CID               : in  std_logic_vector(3 downto 0);   -- Carrier ID
    MID               : in  std_logic_vector(3 downto 0);   -- Module ID
-- UMIs
    UMI_IN            : in  std_logic_vector(3 downto 0);
    UMI_OUT           : out std_logic_vector(3 downto 0);
    UMI_EN            : out std_logic_vector(3 downto 0);
-- READ FIFO CLK
    FCLK_RD           : in  std_logic;                      -- FIFO_IN clock to be used in this module (only when FCLK_G_DOMAIN=FALSE)
    SRC_FCLK_RD       : out std_logic;                      -- FIFO_IN clock source for the top level  (only when FCLK_G_DOMAIN=FALSE)
-- WRITE FIFO CLK
    FCLK_WR           : in  std_logic;                      -- FIFO_OUT clock to be used in this module (only when FCLK_G_DOMAIN=FALSE)
    SRC_FCLK_WR       : out std_logic;                      -- FIFO_OUT clock source for the top level  (only when FCLK_G_DOMAIN=FALSE)
-- COMMON FIFO CLK
    FCLK_G            : in  std_logic;                      -- Common FIFO clock to be used in this module (only when FCLK_G_DOMAIN=TRUE)
    SRC_FCLK_G        : out std_logic;                      -- Common FIFO clock source for the top level  (only when FCLK_G_DOMAIN=TRUE)
-- FIFO IN / HE_RD_6F interface
    INFIFO_READ_REQ   : out std_logic_vector(5 downto 0);   -- FIFO_IN Read Request
    INFIFO_DVALID     : in  std_logic_vector(5 downto 0);   -- FIFO_IN Data Valid
    INFIFO_SINGLE     : in  std_logic_vector(5 downto 0);   -- FIFO_IN Single data item available
    INFIFO_BURST      : in  std_logic_vector(5 downto 0);   -- FIFO_IN Block of data available
    INFIFO0_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 0
    INFIFO1_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 1
    INFIFO2_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 2
    INFIFO3_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 3
    INFIFO4_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 4
    INFIFO5_D         : in  std_logic_vector(31 downto 0);  -- FIFO_IN Data for FIFO 5
-- FIFO OUT / HE_WR_6F interface
    OUTFIFO_READY     : in  std_logic_vector(5 downto 0);   -- FIFO_OUT Ready Flag
    OUTFIFO_WRITE     : out std_logic_vector(5 downto 0);   -- FIFO_OUT Write Command
    OUTFIFO_D         : out std_logic_vector(31 downto 0);  -- FIFO_OUT Data
-- SERIAL BUS / HE_USER Message interface
    MSG_CLK           : out std_logic;                      -- HSB clock source for the top level
    MSG_DIN           : in  std_logic_vector(7 downto 0);   -- data received from HSB
    MSG_ADDR          : in  std_logic_vector(7 downto 0);   -- HSB address
    MSG_AEN           : in  std_logic;                      -- address enable
    MSG_WEN           : in  std_logic;                      -- write access
    MSG_REN           : in  std_logic;                      -- read access
    MSG_DONE          : in  std_logic;                      -- message successfully transmitted
    MSG_COUNT         : in  std_logic;                      -- user's counter enable
    MSG_CLEAR         : in  std_logic;                      -- user's counter clear
    MSG_READY         : out std_logic;                      -- to acknowledge an access
    MSG_SEND_MSG      : out std_logic;                      -- message send command
    MSG_CE            : out std_logic;                      -- to control speed operation
    MSG_DOUT          : out std_logic_vector(7 downto 0);   -- data sent to HSB
    MSG_SEND_ID       : out std_logic;                      -- ID information send command
    MSG_LAST_BYTE     : out std_logic;                      -- to indicate when the last byte is presented
-- CONNECTOR DIGITAL IO
    CONN_A_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector A
    CONN_A_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector A
    CONN_A_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector A
    CONN_B_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector B
    CONN_B_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector B
    CONN_B_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector B
    CONN_C_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector C
    CONN_C_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector C
    CONN_C_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector C
    CONN_D_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector D
    CONN_D_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector D
    CONN_D_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector D
    CONN_E_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector E
    CONN_E_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector E
    CONN_E_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector E
    CONN_F_IN         : in  std_logic_vector(29 downto 0);  -- Data input on Connector F
    CONN_F_OUT        : out std_logic_vector(29 downto 0);  -- Data output on Connector F
    CONN_F_EN         : out std_logic_vector(29 downto 0);  -- Output enables for Connector F
-- DDR User Clock A
    DDR_A_USER_CLK    : out std_logic;                      -- DDR Port A Clock source
-- DDR User Reset A
    DDR_A_USER_RST    : out std_logic;                      -- DDR Port A Data Count Reset
-- DDR Data Count
    DDR_A_DATA_COUNT  : in  std_logic_vector(31 downto 0);  -- DDR Port A Data Count
-- DDR Write Port A
    DDR_A_WR_DATA     : out std_logic_vector(71 downto 0);  -- DDR Port A Write Data
    DDR_A_WR_ADDR     : out std_logic_vector(24 downto 0);  -- DDR Port A Write Address
    DDR_A_WR_ADDR_WEN : out std_logic;                      -- DDR Port A Wr-Address Enable
    DDR_A_WR_ADDR_FF  : in  std_logic;                      -- DDR Port A Wr-Address Full Flag
    DDR_A_WR_ADDR_AF  : in  std_logic;                      -- DDR Port A Wr-Address Almost Full
    DDR_A_WR_RISE_WEN : out std_logic;                      -- DDR Port A Rising Data Enable
    DDR_A_WR_RISE_FF  : in  std_logic;                      -- DDR Port A Rising Data Full Flag
    DDR_A_WR_RISE_AF  : in  std_logic;                      -- DDR Port A Rising Data Almost Full
    DDR_A_WR_FALL_WEN : out std_logic;                      -- DDR Port A Falling Data Enable
    DDR_A_WR_FALL_FF  : in  std_logic;                      -- DDR Port A Falling Data Full Flag
    DDR_A_WR_FALL_AF  : in  std_logic;                      -- DDR Port A Falling Data Almost Full
    DDR_A_WR_DM_WEN   : out std_logic;                      -- DDR Port A Data Mask Enable
    DDR_A_WR_DM_FF    : in  std_logic;                      -- DDR Port A Data Mask Full Flag
    DDR_A_WR_DM_AF    : in  std_logic;                      -- DDR Port A Data Mask Almost Full
-- DDR Read Port A
    DDR_A_RD_DATA     : in  std_logic_vector(63 downto 0);  -- DDR Port A Read Data
    DDR_A_RD_ADDR     : out std_logic_vector(24 downto 0);  -- DDR Port A Read Address
    DDR_A_RD_ADDR_WEN : out std_logic;                      -- DDR Port A Rd-Address Enable
    DDR_A_RD_ADDR_FF  : in  std_logic;                      -- DDR Port A Rd-Address Full Flag
    DDR_A_RD_ADDR_AF  : in  std_logic;                      -- DDR Port A Rd-Address Almost Full
    DDR_A_RD_RISE_REN : out std_logic;                      -- DDR Port A Rising Data Enable
    DDR_A_RD_RISE_EF  : in  std_logic;                      -- DDR Port A Rising Data Empty Flag
    DDR_A_RD_RISE_AE  : in  std_logic;                      -- DDR Port A Rising Data Almost Empty
    DDR_A_RD_FALL_REN : out std_logic;                      -- DDR Port A Falling Data Enable
    DDR_A_RD_FALL_EF  : in  std_logic;                      -- DDR Port A Falling Data Empty Flag
    DDR_A_RD_FALL_AE  : in  std_logic                       -- DDR Port A Falling Data Almost Empty
  );
end USER_AP;


architecture EXAMPLE1 of USER_AP is

  component HSB1
    port (
      RST         : in  std_logic;
      CLK         : in  std_logic;
      DIN         : in  std_logic_vector(7 downto 0);
      ADDR        : in  std_logic_vector(7 downto 0);
      AEN         : in  std_logic;
      WEN         : in  std_logic;
      REN         : in  std_logic;
      DONE        : in  std_logic;
      COUNT       : in  std_logic;
      CLEAR       : in  std_logic;
      READY       : out std_logic;
      SEND_MSG    : out std_logic;
      CE          : out std_logic;
      DOUT        : out std_logic_vector(7 downto 0);
      SEND_ID     : out std_logic;
      LAST_BYTE   : out std_logic;
      --
      INFIFO_SEL  : out std_logic_vector (5 downto 0);
      OUTFIFO_SEL : out std_logic_vector (5 downto 0)
    );
  end component;

  component fifo15x32
    port (
      din          : in  std_logic_vector(31 downto 0);
      wr_en        : in  std_logic;
      wr_clk       : in  std_logic;
      rd_en        : in  std_logic;
      rd_clk       : in  std_logic;
      ainit        : in  std_logic;
      dout         : out std_logic_vector(31 downto 0);
      full         : out std_logic;
      empty        : out std_logic;
      almost_full  : out std_logic;
      almost_empty : out std_logic
    );
  end component;

  component BUFG
    port(I : in  std_logic;
         O : out std_logic);
  end component;

  signal MCLK        : std_logic;  -- Main clock
  signal LEDcount    : unsigned(25 downto 0);
  signal MUX_SEL     : std_logic_vector(2 downto 0);
  signal INFIFO_SEL  : std_logic_vector(5 downto 0);
  signal OUTFIFO_SEL : std_logic_vector(5 downto 0);
  --
  signal FIFO_A      : std_logic_vector(31 downto 0);
  signal FIFO_B      : std_logic_vector(31 downto 0);
  signal FIFO_C      : std_logic_vector(31 downto 0);
  signal FIFO_D      : std_logic_vector(31 downto 0);
  signal FIFO_E      : std_logic_vector(31 downto 0);
  signal FIFO_F      : std_logic_vector(31 downto 0);
  signal FIFO_G      : std_logic_vector(31 downto 0);
  signal FIFO_AF     : std_logic_vector(5 downto 0);
  signal FIFO_EF     : std_logic_vector(5 downto 0);
  signal FIFO_RD     : std_logic_vector(5 downto 0);
  -- Control signals for transfer from FIFOs A-F to FIFO G
  signal NOT_EMPTY_A : std_logic;
  signal NOT_EMPTY_B : std_logic;
  signal NOT_EMPTY_C : std_logic;
  signal WR_EN       : std_logic;
  signal AF          : std_logic;
  signal AF_v        : std_logic_vector(5 downto 0);
  -- Control signals for transfer from FIFO G to HERON FIFO-Write Interface
  signal READY_A     : std_logic;
  signal READY_B     : std_logic;
  signal READY_C     : std_logic;
  signal RD_EN       : std_logic;
  signal EMPTY       : std_logic;
  signal EMPTY_v     : std_logic_vector(5 downto 0);
  signal WRITE       : std_logic_vector(5 downto 0);

  signal OSC3_CLK    : std_logic;

begin

  -- ==========================================================
  -- ==========================================================
  --       <<<<<<<   INSERT YOUR CODE HERE    >>>>>>>>>
  -- ==========================================================
  -- ==========================================================


  -------------------------------------------------------------
  -- Main clock to be used in this example

  iOSC3_BUFG : BUFG port map (I=>OSC3, O=>OSC3_CLK);

  MCLK <= OSC3_CLK;

  -------------------------------------------------------------
  -- Drive the UDP-RESET high (inactive)

  UDPRES <= '1';

  -------------------------------------------------------------
  -- Drive the MODULE HAS PROCESSOR signal high (inactive)

  MOD_HAS_PROC <= '1';

  -------------------------------------------------------------
  -- Drive unused signals

  UMI_OUT <= (others=>'0');
  UMI_EN  <= (others=>'1');

  -------------------------------------------------------------
  -- FIFOs

  SRC_FCLK_RD <= '0';   -- clock source for READ FIFO
  SRC_FCLK_WR <= '0';   -- clock source for WRITE FIFO
  SRC_FCLK_G  <= MCLK;  -- global clock source for both FIFOs

  INFIFO_READ_REQ <= NOT FIFO_AF;

  iFIFO0 : fifo15x32
    port map (
      din          => INFIFO0_D,
      wr_en        => INFIFO_DVALID(0),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(0),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_A,
      full         => open,
      empty        => FIFO_EF(0),
      almost_full  => FIFO_AF(0),
      almost_empty => open );

  iFIFO1 : fifo15x32
    port map (
      din          => INFIFO1_D,
      wr_en        => INFIFO_DVALID(1),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(1),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_B,
      full         => open,
      empty        => FIFO_EF(1),
      almost_full  => FIFO_AF(1),
      almost_empty => open );

  iFIFO2 : fifo15x32
    port map (
      din          => INFIFO2_D,
      wr_en        => INFIFO_DVALID(2),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(2),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_C,
      full         => open,
      empty        => FIFO_EF(2),
      almost_full  => FIFO_AF(2),
      almost_empty => open );

  iFIFO3 : fifo15x32
    port map (
      din          => INFIFO3_D,
      wr_en        => INFIFO_DVALID(3),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(3),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_D,
      full         => open,
      empty        => FIFO_EF(3),
      almost_full  => FIFO_AF(3),
      almost_empty => open );

  iFIFO4 : fifo15x32
    port map (
      din          => INFIFO4_D,
      wr_en        => INFIFO_DVALID(4),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(4),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_E,
      full         => open,
      empty        => FIFO_EF(4),
      almost_full  => FIFO_AF(4),
      almost_empty => open );

  iFIFO5 : fifo15x32
    port map (
      din          => INFIFO5_D,
      wr_en        => INFIFO_DVALID(5),
      wr_clk       => FCLK_G,
      rd_en        => FIFO_RD(5),
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => FIFO_F,
      full         => open,
      empty        => FIFO_EF(5),
      almost_full  => FIFO_AF(5),
      almost_empty => open );

  process(FCLK_G)
  begin
    if rising_edge(FCLK_G) then
      MUX_SEL(0) <= INFIFO_SEL(1) OR INFIFO_SEL(3) OR INFIFO_SEL(5);
      MUX_SEL(1) <= INFIFO_SEL(2) OR INFIFO_SEL(3);
      MUX_SEL(2) <= INFIFO_SEL(4) OR INFIFO_SEL(5);
    end if;
  end process;

  process (MUX_SEL, FIFO_A, FIFO_B, FIFO_C, FIFO_D, FIFO_E, FIFO_F)
  begin
    case MUX_SEL is
      when "000"  => FIFO_G <= FIFO_A;
      when "001"  => FIFO_G <= FIFO_B;
      when "010"  => FIFO_G <= FIFO_C;
      when "011"  => FIFO_G <= FIFO_D;
      when "100"  => FIFO_G <= FIFO_E;
      when "101"  => FIFO_G <= FIFO_F;
      when others => FIFO_G <= (others=>'0');
    end case;
  end process;

  AF_v <= AF & AF & AF & AF & AF & AF;

  FIFO_RD <= (NOT FIFO_EF) AND (NOT AF_v) AND INFIFO_SEL;

  NOT_EMPTY_A <= ((NOT FIFO_EF(0)) AND INFIFO_SEL(0)) OR
                 ((NOT FIFO_EF(1)) AND INFIFO_SEL(1));

  NOT_EMPTY_B <= ((NOT FIFO_EF(2)) AND INFIFO_SEL(2)) OR
                 ((NOT FIFO_EF(3)) AND INFIFO_SEL(3));

  NOT_EMPTY_C <= ((NOT FIFO_EF(4)) AND INFIFO_SEL(4)) OR
                 ((NOT FIFO_EF(5)) AND INFIFO_SEL(5));

  process(RESET, FCLK_G)
  begin
    if RESET='1' then
      WR_EN  <= '0';
    elsif rising_edge(FCLK_G) then
      WR_EN <= '0';
      if (NOT_EMPTY_A='1' or NOT_EMPTY_B='1' or NOT_EMPTY_C='1') and AF='0' then
        WR_EN <= '1';
      end if;
    end if;
  end process;

  iFIFO6 : fifo15x32
    port map (
      din          => FIFO_G,
      wr_en        => WR_EN,
      wr_clk       => FCLK_G,
      rd_en        => RD_EN,
      rd_clk       => FCLK_G,
      ainit        => RESET,
      dout         => OUTFIFO_D,
      full         => open,
      empty        => EMPTY,
      almost_full  => AF,
      almost_empty => open );

  READY_A <= (OUTFIFO_READY(0) AND OUTFIFO_SEL(0)) OR
             (OUTFIFO_READY(1) AND OUTFIFO_SEL(1));

  READY_B <= (OUTFIFO_READY(2) AND OUTFIFO_SEL(2)) OR
             (OUTFIFO_READY(3) AND OUTFIFO_SEL(3));

  READY_C <= (OUTFIFO_READY(4) AND OUTFIFO_SEL(4)) OR
             (OUTFIFO_READY(5) AND OUTFIFO_SEL(5));

  RD_EN <= (READY_A OR READY_B OR READY_C) AND (NOT EMPTY);

  EMPTY_v <= EMPTY & EMPTY & EMPTY & EMPTY & EMPTY & EMPTY;

  WRITE <= (NOT EMPTY_v) AND OUTFIFO_READY AND OUTFIFO_SEL;

  process(RESET, FCLK_G)
  begin
    if RESET='1' then
      OUTFIFO_WRITE <= (others=>'0');
    elsif rising_edge(FCLK_G) then
      OUTFIFO_WRITE <= WRITE;
    end if;
  end process;

  -------------------------------------------------------------
  -- DDR SDRAM (not used in this example)

  DDR_A_USER_CLK    <= '0';
  DDR_A_USER_RST    <= '0';

  DDR_A_WR_DATA     <= (others=>'0');
  DDR_A_WR_ADDR     <= (others=>'0');
  DDR_A_WR_ADDR_WEN <= '0';
  DDR_A_WR_RISE_WEN <= '0';
  DDR_A_WR_FALL_WEN <= '0';
  DDR_A_WR_DM_WEN   <= '0';

  DDR_A_RD_ADDR     <= (others=>'0');
  DDR_A_RD_ADDR_WEN <= '0';
  DDR_A_RD_RISE_REN <= '0';
  DDR_A_RD_FALL_REN <= '0';

  -------------------------------------------------------------
  -- Serial Bus

  MSG_CLK <= OSC3_CLK;  -- clock for Message Interface

  iHSB1 : HSB1
    port map (
      RST         => RESET,
      CLK         => OSC3_CLK,
      DIN         => MSG_DIN,
      ADDR        => MSG_ADDR,
      AEN         => MSG_AEN,
      WEN         => MSG_WEN,
      REN         => MSG_REN,
      DONE        => MSG_DONE,
      COUNT       => MSG_COUNT,
      CLEAR       => MSG_CLEAR,
      READY       => MSG_READY,
      SEND_MSG    => MSG_SEND_MSG,
      CE          => MSG_CE,
      DOUT        => MSG_DOUT,
      SEND_ID     => MSG_SEND_ID,
      LAST_BYTE   => MSG_LAST_BYTE,
      INFIFO_SEL  => INFIFO_SEL,
      OUTFIFO_SEL => OUTFIFO_SEL );

  -------------------------------------------------------------
  -- Connector Digital IO (not used in this example)

  CONN_A_OUT <= (others=>'0');
  CONN_A_EN  <= (others=>'1');

  CONN_B_OUT <= (others=>'0');
  CONN_B_EN  <= (others=>'1');

  CONN_C_OUT <= (others=>'0');
  CONN_C_EN  <= (others=>'1');

  CONN_D_OUT <= (others=>'0');
  CONN_D_EN  <= (others=>'1');

  CONN_E_OUT <= (others=>'0');
  CONN_E_EN  <= (others=>'1');

  CONN_F_OUT <= (others=>'0');
  CONN_F_EN  <= (others=>'1');

  -------------------------------------------------------------
  -- Led Flasher : dividing F_CLKG clock by 2**24

  process(RESET, FCLK_G)
  begin
    if RESET='1' then
      LEDcount <= (others=>'0');
    elsif rising_edge(FCLK_G) then
      LEDcount <= LEDcount + 1;
    end if;
  end process;

  LED(4) <= LEDcount(24);

  -- Drive LEDs high (inactive)
  LED(3 downto 0) <= (others=>'1');

end EXAMPLE1;
