-- ==============================================================
-- FILE : HE_WR_6F.VHD  -  DO NOT EDIT THIS FILE
-- ==============================================================
--
-- This file is part of the Hardware Interface Layer (H.I.L) of
-- your project when using your HERON-FPGA14 module.
--
-- This file must NOT be modified by users of the Module.
--
-- ==============================================================
--
--  Module      : HE_WR_6F
--  Date        : 01/07/2004
--  Author      : R. Williams - HUNT ENGINEERING
--  Description : Output FIFO interface, for 6 FIFOs
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    28-02-02    First Written
--  1.1     R. Williams    08-05-02    Syntax change made to all
--                                     instanciated components,
--                                     (changed '0' to GND)
--                                     for compatibility with
--                                     ModelSim5.5b.
--  1.2     R. Williams    11-06-02    Added 1ns delay on paths
--                                     from inferred flip-flops
--                                     to instantiated flip-flops
--                                     to prevent setup violations
--                                     in functional simulation.
--  2.0     R. Williams    10-10-02    New components added for
--                                     interfacing to all six HERON
--                                     input FIFOs and all six HERON
--                                     output FIFOs at the same time.
--                                     Added component HE_RD_6F in
--                                     place of component HE_RD_1F.
--                                     Added component HE_WR_6F in
--                                     place of component HE_WR_1F.
--  2.1     R. Williams    20-01-03    Changes made to the HSB
--                                     mastering functions, and 
--                                     additional registering added
--                                     to the AE flag to ensure
--                                     correct reading from HEPC8s.
--
-- ==============================================================


library IEEE;
  use IEEE.std_logic_1164.all;

-- synopsys translate_off
library UNISIM;
  use UNISIM.vcomponents.all;
-- synopsys translate_on

entity HE_WR_6F is
  port (
    -- External PADS - HE_IO_CO
    DOF_FF        : in  std_logic_vector(5 downto 0);
    DOF_AF        : in  std_logic_vector(5 downto 0);
    DOF_WEN       : out std_logic_vector(5 downto 0);
    -- External PADS - HE_IO_DO
    DO            : out std_logic_vector(31 downto 0);
    -- Module I/Os
    RST           : in  std_logic;
    CLK           : in  std_logic;
    OUTFIFO_WRITE : in  std_logic_vector(5 downto 0);
    OUTFIFO_D     : in  std_logic_vector(31 downto 0);
    OUTFIFO_READY : out std_logic_vector(5 downto 0)
  );
end HE_WR_6F;


architecture RTL of HE_WR_6F is

  component FD
    port(
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic );
  end component;

  component FDC
    port(
      Q   : out std_logic;
      D   : in  std_logic;
      C   : in  std_logic;
      CLR : in  std_logic );
  end component;

  -- Note : attributes on instances are supported by all synthesis tools.

  attribute LOC : string;
  attribute IOB : string;

  attribute LOC of iFF0  : label is "ILOGIC_X*Y*";
  attribute LOC of iFF1  : label is "ILOGIC_X*Y*";
  attribute LOC of iFF2  : label is "ILOGIC_X*Y*";
  attribute LOC of iFF3  : label is "ILOGIC_X*Y*";
  attribute LOC of iFF4  : label is "ILOGIC_X*Y*";
  attribute LOC of iFF5  : label is "ILOGIC_X*Y*";

  attribute LOC of iAF0  : label is "ILOGIC_X*Y*";
  attribute LOC of iAF1  : label is "ILOGIC_X*Y*";
  attribute LOC of iAF2  : label is "ILOGIC_X*Y*";
  attribute LOC of iAF3  : label is "ILOGIC_X*Y*";
  attribute LOC of iAF4  : label is "ILOGIC_X*Y*";
  attribute LOC of iAF5  : label is "ILOGIC_X*Y*";

  attribute LOC of iWE0  : label is "OLOGIC_X*Y*";
  attribute LOC of iWE1  : label is "OLOGIC_X*Y*";
  attribute LOC of iWE2  : label is "OLOGIC_X*Y*";
  attribute LOC of iWE3  : label is "OLOGIC_X*Y*";
  attribute LOC of iWE4  : label is "OLOGIC_X*Y*";
  attribute LOC of iWE5  : label is "OLOGIC_X*Y*";

  attribute LOC of iDO0  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO1  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO2  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO3  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO4  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO5  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO6  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO7  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO8  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO9  : label is "OLOGIC_X*Y*";
  attribute LOC of iDO10 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO11 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO12 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO13 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO14 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO15 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO16 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO17 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO18 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO19 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO20 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO21 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO22 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO23 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO24 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO25 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO26 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO27 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO28 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO29 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO30 : label is "OLOGIC_X*Y*";
  attribute LOC of iDO31 : label is "OLOGIC_X*Y*";

  attribute IOB of iFF0  : label is "TRUE";
  attribute IOB of iFF1  : label is "TRUE";
  attribute IOB of iFF2  : label is "TRUE";
  attribute IOB of iFF3  : label is "TRUE";
  attribute IOB of iFF4  : label is "TRUE";
  attribute IOB of iFF5  : label is "TRUE";

  attribute IOB of iAF0  : label is "TRUE";
  attribute IOB of iAF1  : label is "TRUE";
  attribute IOB of iAF2  : label is "TRUE";
  attribute IOB of iAF3  : label is "TRUE";
  attribute IOB of iAF4  : label is "TRUE";
  attribute IOB of iAF5  : label is "TRUE";

  attribute IOB of iWE0  : label is "TRUE";
  attribute IOB of iWE1  : label is "TRUE";
  attribute IOB of iWE2  : label is "TRUE";
  attribute IOB of iWE3  : label is "TRUE";
  attribute IOB of iWE4  : label is "TRUE";
  attribute IOB of iWE5  : label is "TRUE";

  attribute IOB of iDO0  : label is "TRUE";
  attribute IOB of iDO1  : label is "TRUE";
  attribute IOB of iDO2  : label is "TRUE";
  attribute IOB of iDO3  : label is "TRUE";
  attribute IOB of iDO4  : label is "TRUE";
  attribute IOB of iDO5  : label is "TRUE";
  attribute IOB of iDO6  : label is "TRUE";
  attribute IOB of iDO7  : label is "TRUE";

  attribute IOB of iDO8  : label is "TRUE";
  attribute IOB of iDO9  : label is "TRUE";
  attribute IOB of iDO10 : label is "TRUE";
  attribute IOB of iDO11 : label is "TRUE";
  attribute IOB of iDO12 : label is "TRUE";
  attribute IOB of iDO13 : label is "TRUE";
  attribute IOB of iDO14 : label is "TRUE";
  attribute IOB of iDO15 : label is "TRUE";

  attribute IOB of iDO16 : label is "TRUE";
  attribute IOB of iDO17 : label is "TRUE";
  attribute IOB of iDO18 : label is "TRUE";
  attribute IOB of iDO19 : label is "TRUE";
  attribute IOB of iDO20 : label is "TRUE";
  attribute IOB of iDO21 : label is "TRUE";
  attribute IOB of iDO22 : label is "TRUE";
  attribute IOB of iDO23 : label is "TRUE";

  attribute IOB of iDO24 : label is "TRUE";
  attribute IOB of iDO25 : label is "TRUE";
  attribute IOB of iDO26 : label is "TRUE";
  attribute IOB of iDO27 : label is "TRUE";
  attribute IOB of iDO28 : label is "TRUE";
  attribute IOB of iDO29 : label is "TRUE";
  attribute IOB of iDO30 : label is "TRUE";
  attribute IOB of iDO31 : label is "TRUE";

  signal GND      : std_logic;
  signal WENc     : std_logic_vector(5 downto 0);
  signal WEN      : std_logic_vector(5 downto 0);
  signal WR_OK    : std_logic_vector(5 downto 0);
  signal FF_REG   : std_logic_vector(5 downto 0);
  signal AF_REG   : std_logic_vector(5 downto 0);
  signal READY    : std_logic_vector(5 downto 0);
  signal DATA_OUT : std_logic_vector(31 downto 0);

begin

  -- HE_IO_CO
  -- ========

  GND <= '0';

  -- Instanciate these flip-flops to ensure they will always be IFDs
  iFF0 : FD port map (FF_REG(0),  D=>DOF_FF(0),  C=>CLK);  -- IOB
  iFF1 : FD port map (FF_REG(1),  D=>DOF_FF(1),  C=>CLK);  -- IOB
  iFF2 : FD port map (FF_REG(2),  D=>DOF_FF(2),  C=>CLK);  -- IOB
  iFF3 : FD port map (FF_REG(3),  D=>DOF_FF(3),  C=>CLK);  -- IOB
  iFF4 : FD port map (FF_REG(4),  D=>DOF_FF(4),  C=>CLK);  -- IOB
  iFF5 : FD port map (FF_REG(5),  D=>DOF_FF(5),  C=>CLK);  -- IOB

  -- Instanciate these flip-flops to ensure they will always be IFDs
  iAF0 : FD port map (AF_REG(0),  D=>DOF_AF(0),  C=>CLK);  -- IOB
  iAF1 : FD port map (AF_REG(1),  D=>DOF_AF(1),  C=>CLK);  -- IOB
  iAF2 : FD port map (AF_REG(2),  D=>DOF_AF(2),  C=>CLK);  -- IOB
  iAF3 : FD port map (AF_REG(3),  D=>DOF_AF(3),  C=>CLK);  -- IOB
  iAF4 : FD port map (AF_REG(4),  D=>DOF_AF(4),  C=>CLK);  -- IOB
  iAF5 : FD port map (AF_REG(5),  D=>DOF_AF(5),  C=>CLK);  -- IOB

  DOF_WEN <= WEN;  -- OBUF_F_8 (instanciation in the top level)

  process(RST, CLK)
  begin
    if RST='1' then
      WR_OK <= (others=>'0');
      READY <= (others=>'0');
    elsif rising_edge(CLK) then
      WR_OK <= READY OR (WR_OK AND (NOT OUTFIFO_WRITE));
      READY <= AF_REG;
    end if;
  end process;

  WENc <= (OUTFIFO_WRITE AND WR_OK) after 1 ns;

  OUTFIFO_READY <= READY after 1 ns;

  -- Instanciate these flip-flops to ensure they will always be OFDs
  iWE0 : FDC port map (WEN(0),  D=>WENc(0),  C=>CLK,  CLR=>RST);  -- IOB
  iWE1 : FDC port map (WEN(1),  D=>WENc(1),  C=>CLK,  CLR=>RST);  -- IOB
  iWE2 : FDC port map (WEN(2),  D=>WENc(2),  C=>CLK,  CLR=>RST);  -- IOB
  iWE3 : FDC port map (WEN(3),  D=>WENc(3),  C=>CLK,  CLR=>RST);  -- IOB
  iWE4 : FDC port map (WEN(4),  D=>WENc(4),  C=>CLK,  CLR=>RST);  -- IOB
  iWE5 : FDC port map (WEN(5),  D=>WENc(5),  C=>CLK,  CLR=>RST);  -- IOB

  DATA_OUT <= OUTFIFO_D after 1 ns;

  -- Instanciate these flip-flops to ensure they will always be IFDs
  iDO0  : FDC port map (DO(0),  D=>DATA_OUT(0),  C=>CLK,  CLR=>GND);  -- IOB
  iDO1  : FDC port map (DO(1),  D=>DATA_OUT(1),  C=>CLK,  CLR=>GND);  -- IOB
  iDO2  : FDC port map (DO(2),  D=>DATA_OUT(2),  C=>CLK,  CLR=>GND);  -- IOB
  iDO3  : FDC port map (DO(3),  D=>DATA_OUT(3),  C=>CLK,  CLR=>GND);  -- IOB
  iDO4  : FDC port map (DO(4),  D=>DATA_OUT(4),  C=>CLK,  CLR=>GND);  -- IOB
  iDO5  : FDC port map (DO(5),  D=>DATA_OUT(5),  C=>CLK,  CLR=>GND);  -- IOB
  iDO6  : FDC port map (DO(6),  D=>DATA_OUT(6),  C=>CLK,  CLR=>GND);  -- IOB
  iDO7  : FDC port map (DO(7),  D=>DATA_OUT(7),  C=>CLK,  CLR=>GND);  -- IOB

  iDO8  : FDC port map (DO(8),  D=>DATA_OUT(8),  C=>CLK,  CLR=>GND);  -- IOB
  iDO9  : FDC port map (DO(9),  D=>DATA_OUT(9),  C=>CLK,  CLR=>GND);  -- IOB
  iDO10 : FDC port map (DO(10), D=>DATA_OUT(10), C=>CLK,  CLR=>GND);  -- IOB
  iDO11 : FDC port map (DO(11), D=>DATA_OUT(11), C=>CLK,  CLR=>GND);  -- IOB
  iDO12 : FDC port map (DO(12), D=>DATA_OUT(12), C=>CLK,  CLR=>GND);  -- IOB
  iDO13 : FDC port map (DO(13), D=>DATA_OUT(13), C=>CLK,  CLR=>GND);  -- IOB
  iDO14 : FDC port map (DO(14), D=>DATA_OUT(14), C=>CLK,  CLR=>GND);  -- IOB
  iDO15 : FDC port map (DO(15), D=>DATA_OUT(15), C=>CLK,  CLR=>GND);  -- IOB

  iDO16 : FDC port map (DO(16), D=>DATA_OUT(16), C=>CLK,  CLR=>GND);  -- IOB
  iDO17 : FDC port map (DO(17), D=>DATA_OUT(17), C=>CLK,  CLR=>GND);  -- IOB
  iDO18 : FDC port map (DO(18), D=>DATA_OUT(18), C=>CLK,  CLR=>GND);  -- IOB
  iDO19 : FDC port map (DO(19), D=>DATA_OUT(19), C=>CLK,  CLR=>GND);  -- IOB
  iDO20 : FDC port map (DO(20), D=>DATA_OUT(20), C=>CLK,  CLR=>GND);  -- IOB
  iDO21 : FDC port map (DO(21), D=>DATA_OUT(21), C=>CLK,  CLR=>GND);  -- IOB
  iDO22 : FDC port map (DO(22), D=>DATA_OUT(22), C=>CLK,  CLR=>GND);  -- IOB
  iDO23 : FDC port map (DO(23), D=>DATA_OUT(23), C=>CLK,  CLR=>GND);  -- IOB

  iDO24 : FDC port map (DO(24), D=>DATA_OUT(24), C=>CLK,  CLR=>GND);  -- IOB
  iDO25 : FDC port map (DO(25), D=>DATA_OUT(25), C=>CLK,  CLR=>GND);  -- IOB
  iDO26 : FDC port map (DO(26), D=>DATA_OUT(26), C=>CLK,  CLR=>GND);  -- IOB
  iDO27 : FDC port map (DO(27), D=>DATA_OUT(27), C=>CLK,  CLR=>GND);  -- IOB
  iDO28 : FDC port map (DO(28), D=>DATA_OUT(28), C=>CLK,  CLR=>GND);  -- IOB
  iDO29 : FDC port map (DO(29), D=>DATA_OUT(29), C=>CLK,  CLR=>GND);  -- IOB
  iDO30 : FDC port map (DO(30), D=>DATA_OUT(30), C=>CLK,  CLR=>GND);  -- IOB
  iDO31 : FDC port map (DO(31), D=>DATA_OUT(31), C=>CLK,  CLR=>GND);  -- IOB

end RTL;

