----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used     --
-- solely for design, simulation, implementation and creation of    --
-- design files limited to Xilinx devices or technologies. Use      --
-- with non-Xilinx devices or technologies is expressly prohibited  --
-- and immediately terminates your license.                         --
--                                                                  --
-- Xilinx products are not intended for use in life support         --
-- appliances, devices, or systems. Use in such applications are    --
-- expressly prohibited.                                            --
--                                                                  --
-- Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           --
----------------------------------------------------------------------

-- You must compile the wrapper file multi24x24.vhd when simulating
-- the core, multi24x24. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY multi24x24 IS
	port (
	clk: IN std_logic;
	a: IN std_logic_VECTOR(23 downto 0);
	b: IN std_logic_VECTOR(23 downto 0);
	q: OUT std_logic_VECTOR(47 downto 0));
END multi24x24;

ARCHITECTURE multi24x24_a OF multi24x24 IS

component wrapped_multi24x24
	port (
	clk: IN std_logic;
	a: IN std_logic_VECTOR(23 downto 0);
	b: IN std_logic_VECTOR(23 downto 0);
	q: OUT std_logic_VECTOR(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_multi24x24 use entity XilinxCoreLib.mult_gen_v3_1(behavioral)
		generic map(
			c_mult_type => 0,
			c_has_load_done => 0,
			c_sync_enable => 1,
			c_has_q => 1,
			c_has_o => 0,
			c_stack_adders => 0,
			c_has_rdy => 0,
			c_has_loadb => 0,
			c_mem_init_prefix => "mem",
			c_mem_type => 0,
			c_out_width => 48,
			c_has_sclr => 0,
			c_has_b => 1,
			c_b_constant => 0,
			c_output_hold => 0,
			bram_addr_width => 9,
			c_pipeline => 1,
			c_a_type => 1,
			c_has_swapb => 0,
			c_sqm_type => 0,
			c_b_type => 1,
			c_has_aclr => 0,
			c_has_nd => 0,
			c_has_rfd => 0,
			c_b_width => 24,
			c_b_value => "10",
			c_baat => 24,
			c_has_a_signed => 0,
			c_enable_rlocs => 0,
			c_a_width => 24,
			c_has_ce => 0,
			c_reg_a_b_inputs => 1,
			c_use_luts => 1);
BEGIN

U0 : wrapped_multi24x24
		port map (
			clk => clk,
			a => a,
			b => b,
			q => q);
END multi24x24_a;

-- synopsys translate_on

