-- ==============================================================
-- FILE : COLOURPICKER.VHD  - may be modified by the USER
-- ==============================================================
--
-- This file is part of the Image Processing Demo, for the HERON-
-- FPGA14 module.
--
-- This file may be modified by the users to implement their
-- own logic.
--
-- ==============================================================
--
--  Module      : colourPicker
--  Date        : 06/04/2006
--  Author      : J. Maddocks - HUNT ENGINEERING
--  Description : Selects odd pixels and odd lines
--
-- ==============================================================
--
--  Ver     Modified By      Date      Changes
--  ---     -----------      ----      -------
--  1.0     R. Williams    06-04-06    Taken from FPGA12 Example.
--  3.1     R. Williams    07-09-07    Changes to CamLink_IF.vhd
--                                     to ensure correct operation
--                                     under ISE9.1.
--
-- ==============================================================


library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity colourPicker is
  port (
    DATA_IN    : in  std_logic_vector(31 downto 0);
    DATA_OUT   : out std_logic_vector(31 downto 0);
    DVALID_IN  : in  std_logic;
    DVALID_OUT : out std_logic;
    CLOCK      : in  std_logic;
    RESET      : in  std_logic;
    EOL_IN     : in  std_logic;
    EOL_OUT    : out std_logic;
    EOF_IN     : in  std_logic;
    EOF_OUT    : out std_logic
  );
end colourPicker;


architecture Behavioral of colourPicker is

  signal pixelPass : std_logic;
  signal linePass  : std_logic;

begin

  process(RESET, CLOCK)
  begin
    if RESET='1' then
      pixelPass <= '0';
    elsif rising_edge(CLOCK) then
      if (EOL_IN='1' or EOF_IN='1') then
        pixelPass <= '0';
      end if;
      if (DVALID_IN='1') then
        pixelPass <= not pixelPass;
      end if;
    end if;
  end process;

  process(RESET, CLOCK)
  begin
    if RESET='1' then
      linePass <= '0';
    elsif rising_edge(CLOCK) then
      if (EOF_IN='1') then
        linePass <= '0';
      elsif(EOL_IN='1') then
        linePass <= not linePass;
      end if;
    end if;
  end process;

  process(CLOCK)
  begin
    if rising_edge(CLOCK) then
      EOL_OUT    <= '0';
      DVALID_OUT <= '0';
      if linePass='1' then
        EOL_OUT <= EOL_IN;
      end if;
      if(linePass='1' and pixelPass='1') then
        DVALID_OUT <= DVALID_IN;
      end if;
    end if;
  end process;

  EOF_OUT  <= EOF_IN;
  DATA_OUT <= DATA_IN;

end Behavioral;
